公开(公告)号：US06570249B1

公开(公告)日：2003-05-27

申请号：US10060811

申请日：2002-01-30

申请人： Chih-Chin Liao ,  Han-PIng Pu ,  Chien-Ping Huang

发明人： Chih-Chin Liao ,  Han-PIng Pu ,  Chien-Ping Huang

IPC分类号： H01L2352

CPC分类号： H01L25/16 ,  H01L23/49575 ,  H01L23/50 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/49171 ,  H01L2924/01015 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device and a fabrication method of the same are proposed, in which at least one electronic component is firstly mounted on a first substrate, and then the first substrate is attached onto a semiconductor chip or a second substrate. Further, with the chip being deposited on the second substrate, electrical connection is established among the first substrate, the second substrate and the chip. This combined structure is subsequently subjected to molding, ball implantation and singulation processes, and thus completes the fabrication of the semiconductor device. Such a semiconductor device provides significant advantages, including prevention of the occurrence of wire short-circuiting, no need to alter the substrate design, no need to use a circuit pattern with fine pitches or an expensive substrate integrated with electronic components.

摘要翻译： 提出了一种半导体器件及其制造方法，其中至少一个电子部件首先安装在第一基板上，然后将第一基板附接到半导体芯片或第二基板上。 此外，由于芯片沉积在第二基板上，所以在第一基板，第二基板和芯片之间建立电连接。 随后对该组合结构进行模制，球注入和分割处理，从而完成半导体器件的制造。 这样的半导体器件提供了显着的优点，包括防止线路短路的发生，不需要改变基板设计，不需要使用具有细间距的电路图案或与电子部件集成的昂贵的基板。

公开(公告)号：US06943439B2

公开(公告)日：2005-09-13

申请号：US10116204

申请日：2002-04-04

申请人： Chien-Ping Huang ,  Han-Ping Pu ,  Chih-Chin Liao

发明人： Chien-Ping Huang ,  Han-Ping Pu ,  Chih-Chin Liao

IPC分类号： H01L21/48 ,  H01L23/498 ,  H01L23/544 ,  H05K1/02 ,  H05K3/24 ,  H05K3/28 ,  H05K3/34 ,  H01L23/02 ,  H01L23/48 ,  H01L23/495 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/85 ,  H01L21/4846 ,  H01L22/34 ,  H01L23/49816 ,  H01L24/48 ,  H01L2224/48 ,  H01L2224/8501 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H05K1/0269 ,  H05K3/242 ,  H05K3/28 ,  H05K3/3489 ,  H05K2201/09781 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A substrate and a fabrication method thereof are proposed, with at least a check point being formed on the substrate. Prior to wire bonding and/or molding processes, cleanness of the substrate (cleaned by plasma) is determined according to color variation of the check point, so as to allow only cleaned and contamination-free substrates to be subsequently formed with bonding wires and encapsulants thereon. Thereby, qualities of wire-bonded electrical connection and encapsulant adhesion for the substrate can be assured, which helps prevent the occurrence of delamination between the encapsulant and the substrate. Moreover, the check point formed on the substrate is made during general substrate fabrication by using current equipment and technique, and in a manner as not to interfere with trace routability on the substrate; thereby, costs and complexity of substrate fabrication would not undesirably increased.

摘要翻译： 提出了一种基板及其制造方法，至少在基板上形成检查点。 在引线接合和/或模制工艺之前，根据检查点的颜色变化确定基材的清洁度（通过等离子体清洁），以便仅使用清洁和无污染的基材随后用接合线和密封剂形成 上。 因此，可以确保线接合电连接的质量和用于衬底的密封剂附着性，这有助于防止密封剂和衬底之间的分层的发生。 此外，通过使用当前的设备和技术，在通常的基板制造中形成的检查点，并且以不干扰基板上的迹线布线性的方式进行; 因此，衬底制造的成本和复杂性将不会不期望地增加。

公开(公告)号：US06689636B2

公开(公告)日：2004-02-10

申请号：US10411457

申请日：2003-04-10

申请人： Chih-Chin Liao ,  Han-PIng Pu ,  Chien-Ping Huang

发明人： Chih-Chin Liao ,  Han-PIng Pu ,  Chien-Ping Huang

IPC分类号： H01L2144

CPC分类号： H01L25/16 ,  H01L23/49575 ,  H01L23/50 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/49171 ,  H01L2924/01015 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device and a fabrication method of the same are proposed, in which at least one electronic component is firstly mounted on a first substrate, and then the first substrate is attached onto a semiconductor chip or a second substrate. Further, with the chip being deposited on the second substrate, electrical connection is established among the first substrate, the second substrate and the chip. This combined structure is subsequently subjected to molding, ball implantation and singulation processes, and thus completes the fabrication of the semiconductor device. Such a semiconductor device provides significant advantages, including prevention of the occurrence of wire short-circuiting, no need to alter the substrate design, no need to use a circuit pattern with fine pitches or an expensive substrate integrated with electronic components.

摘要翻译： 提出了一种半导体器件及其制造方法，其中至少一个电子部件首先安装在第一基板上，然后将第一基板附接到半导体芯片或第二基板上。 此外，由于芯片沉积在第二基板上，所以在第一基板，第二基板和芯片之间建立电连接。 随后对该组合结构进行模制，球注入和分割处理，从而完成半导体器件的制造。 这样的半导体器件提供了显着的优点，包括防止线路短路的发生，不需要改变基板设计，不需要使用具有细间距的电路图案或与电子部件集成的昂贵的基板。

公开(公告)号：US06740978B2

公开(公告)日：2004-05-25

申请号：US10418698

申请日：2003-04-18

申请人： Chien-Ping Huang ,  Chih-Chin Liao ,  Yung-Kang Chu

发明人： Chien-Ping Huang ,  Chih-Chin Liao ,  Yung-Kang Chu

IPC分类号： H01L2348

CPC分类号： H01L23/49838 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10161 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor chip package is formed to be capable of reducing moisture erosion by configuring the bonding finger, the plating-conduction-line, and the trace on the chip carrier therein in such a way that the length of path for moisture to penetrate and to reach the bonding finger through a plating-conduction-line is significantly longer than those implemented in a conventional chip package.

摘要翻译： 半导体芯片封装形成为能够通过将粘合指状物，电镀导电线和芯片载体上的迹线配置在其中，使得水分穿过并达到的路径长度来减少水分侵蚀 通过电镀导通线的接合指针显着地长于在常规芯片封装中实现的那些。

公开(公告)号：US06593658B2

公开(公告)日：2003-07-15

申请号：US10001862

申请日：2001-11-19

申请人： Chien-Ping Huang ,  Chih-Chin Liao ,  Yung-Kang Chu

发明人： Chien-Ping Huang ,  Chih-Chin Liao ,  Yung-Kang Chu

IPC分类号： H01L2348

CPC分类号： H01L23/49838 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10161 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor chip package is formed to be capable of reducing moisture erosion by configuring the bonding finger, the plating-conduction-line, and the trace on the chip carrier therein in such a way that the length of path for moisture to penetrate and to reach the bonding finger through a plating-conduction-line is significantly longer than those implemented in a conventional chip package.

公开(公告)号：US07967184B2

公开(公告)日：2011-06-28

申请号：US11280419

申请日：2005-11-16

申请人： Chih-Chin Liao ,  Ken Jian Ming Wang ,  Han-Shiao Chen ,  Chin-Tien Chiu ,  Jack Chang Chien ,  Shrikar Bhagath ,  Cheemen Yu ,  Hem Takiar

发明人： Chih-Chin Liao ,  Ken Jian Ming Wang ,  Han-Shiao Chen ,  Chin-Tien Chiu ,  Jack Chang Chien ,  Shrikar Bhagath ,  Cheemen Yu ,  Hem Takiar

IPC分类号： B23K31/02

CPC分类号： H05K1/111 ,  H01L2224/48091 ,  H01L2224/48227 ,  H05K3/3421 ,  H05K3/3442 ,  H05K3/3452 ,  H05K2201/09427 ,  H05K2201/09663 ,  H05K2201/0989 ,  H05K2201/099 ,  H05K2201/10636 ,  H05K2201/10689 ,  H05K2201/10727 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00014

摘要： A semiconductor package having a low profile is disclosed. In embodiments, a surface mounted component may be mounted directly to the core of the semiconductor package substrate, so that there is no conductive layer, plating layers or solder paste between the component and the substrate core. The surface mounted component may be any type of component which may be surface mounted on a substrate according to an SMT process, including for example passive components and various packaged semiconductors.

摘要翻译： 公开了一种具有低轮廓的半导体封装。 在实施例中，表面安装部件可以直接安装到半导体封装基板的芯部，使得在部件和基板芯之间不存在导电层，镀层或焊膏。 表面安装部件可以是根据SMT工艺可以表面安装在基板上的任何类型的部件，包括例如无源部件和各种封装半导体。

公开(公告)号：US07772107B2

公开(公告)日：2010-08-10

申请号：US11538220

申请日：2006-10-03

申请人： Cheemen Yu ,  Hem Takiar ,  Chih-Chin Liao

发明人： Cheemen Yu ,  Hem Takiar ,  Chih-Chin Liao

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L21/4846 ,  H01L21/486 ,  H01L23/49827 ,  H01L2224/48091 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/00014

摘要： Methods of forming a semiconductor package including a single-sided substrate are disclosed. In a first embodiment of the present invention, a substrate may include a conductive layer on a top surface of the substrate, i.e., on the same side of the substrate as where the die are mounted. In a second embodiment of the present invention, a substrate may include a conductive layer on a bottom of the substrate, i.e., on the opposite side of the substrate as where the die are mounted.

摘要翻译： 公开了形成包括单面基板的半导体封装的方法。 在本发明的第一实施例中，衬底可以在衬底的顶表面上，即在衬底的与安装裸片相同的一侧上包括导电层。 在本发明的第二实施例中，衬底可以包括在衬底的底部上的导电层，即衬底的安装模具的相反侧。

公开(公告)号：US20080305577A1

公开(公告)日：2008-12-11

申请号：US11760385

申请日：2007-06-08

申请人： Chih-Chin Liao ,  Ning Ye ,  Cheemen Yu ,  Jack Chang Chien ,  Hem Takiar

发明人： Chih-Chin Liao ,  Ning Ye ,  Cheemen Yu ,  Jack Chang Chien ,  Hem Takiar

IPC分类号： H01L21/00

CPC分类号： H05K3/242 ,  H01L21/4846 ,  H01L23/49838 ,  H01L23/49855 ,  H01L2224/48227 ,  H01L2924/10253 ,  H01L2924/19105 ,  H05K1/117 ,  H05K3/0052 ,  H05K2203/175 ,  H01L2924/00

摘要： A semiconductor die substrate panel is disclosed including a minimum kerf width between adjoining semiconductor package outlines on the panel, while ensuring electrical isolation of plated electrical terminals. By reducing the width of a boundary between adjoining package outlines, additional space is gained on a substrate panel for semiconductor packages.

摘要翻译： 公开了半导体管芯衬底面板，其包括在面板上相邻的半导体封装轮廓之间的最小间隙宽度，同时确保电镀电端子的电隔离。 通过减小相邻封装轮廓之间的边界的宽度，在用于半导体封装的衬底面板上获得额外的空间。

公开(公告)号：US20070269929A1

公开(公告)日：2007-11-22

申请号：US11435954

申请日：2006-05-17

申请人： Chih-Chin Liao ,  Han-Shiao Chen ,  Chin-Tien Chiu ,  Cheemen Yu ,  Hem Takiar

发明人： Chih-Chin Liao ,  Han-Shiao Chen ,  Chin-Tien Chiu ,  Cheemen Yu ,  Hem Takiar

IPC分类号： H01L21/00 ,  H01L21/31

CPC分类号： H01L23/49838 ,  H01L2924/0002 ,  H05K1/0271 ,  H05K3/243 ,  H05K3/28 ,  H05K2201/09781 ,  H01L2924/00

摘要： A substrate, and a semiconductor die package formed therefrom, are disclosed which include a distributed plating pattern for reducing mechanical stress on the semiconductor die. The substrate according to embodiments of the invention may include traces and contact pads plated in a double image plating process. Additionally, the substrate may include dummy plating areas including plating material. The plated vias and/or traces and the plating material within the dummy plating areas provide a plating pattern which is evenly distributed across the surface of the substrate. The even distribution of the plating pattern prevents peaks and valleys in the finished substrate.

摘要翻译： 公开了一种基板和由其形成的半导体管芯封装，其包括用于减小半导体管芯上的机械应力的分布电镀图案。 根据本发明的实施例的衬底可以包括以双映像电镀工艺电镀的迹线和接触焊盘。 此外，基板可以包括包括电镀材料的虚拟电镀区域。 电镀通孔和/或迹线以及虚拟电镀区域内的电镀材料提供均匀分布在基板表面上的电镀图案。 电镀图案的均匀分布防止成品基板中的峰和谷。

公开(公告)号：US06531762B1

公开(公告)日：2003-03-11

申请号：US09992993

申请日：2001-11-14

申请人： Chih-Chin Liao ,  Kuan-Cheng Chen

发明人： Chih-Chin Liao ,  Kuan-Cheng Chen

IPC分类号： H01L23495

CPC分类号： H01L24/48 ,  H01L23/49838 ,  H01L24/45 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/4911 ,  H01L2224/4912 ,  H01L2224/49171 ,  H01L2224/4943 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A semiconductor package is proposed, in which a substrate is formed with a chip bonding area and a plurality of bond fingers surrounding the chip bonding area, and a plurality of bridging elements are disposed in a stagger manner between the chip bonding area and the bond fingers on the substrate. Multiple wire bonding processes are performed to bond first gold wires between the chip and the bridging elements, and bond second gold wires between the bridging elements and the bond fingers. This therefore significantly shortens a wire bonding distance as compared with only one time of wire bonding for electrically connecting the chip to the substrate. As a result, wire bond operability is improved, and the shortened wire bonding distance reduces wire length so as to enhance resistance of the gold wires to mold flow impact during molding, thereby preventing wire sweeping or wire sagging from occurrence.

摘要翻译： 提出了一种半导体封装，其中衬底形成有芯片接合区域和围绕芯片接合区域的多个键合键，并且多个桥接元件以交错的方式设置在芯片接合区域和结合指状物之间 在基板上。 执行多引线接合工艺以将芯片和桥接元件之间的第一金线接合，并且将桥接元件和键合指之间的第二金线接合。 因此，与用于将芯片电连接到衬底的引线接合的时间相比，这显着缩短了引线接合距离。 结果，提高了引线接合可操作性，并且缩短的引线接合距离减小了线长度，从而提高了金线在成型过程中模具流动冲击的阻力，从而防止电线清扫或线下垂发生。