公开(公告)号：US08605032B2

公开(公告)日：2013-12-10

申请号：US13172854

申请日：2011-06-30

申请人： Chun-Ting Liu ,  Hsu-Ping Tseng ,  Yao-Jen Hsieh ,  Chi-Mao Hung

发明人： Chun-Ting Liu ,  Hsu-Ping Tseng ,  Yao-Jen Hsieh ,  Chi-Mao Hung

IPC分类号： G09G3/34

CPC分类号： G09G3/344 ,  G09G2310/06 ,  G09G2360/16

摘要： An electrophoretic display and a driving method thereof are provided. The electrophoretic display includes a display panel, a storage unit, a timing controller (TCON). The display panel has a plurality of sub-pixels. The storage unit stores a plurality sets of driving waveforms, wherein the lengths of driving waveforms in the sets of driving waveforms are different from each other. The TCON has an analysis module, couples to the display panel and the storage unit, and receives an image signal having a plurality of display data. The analysis module analyzes the display data to obtain a analysis result. The TCON selects one of the sets of driving waveforms according to the analysis result, and drives the sub-pixels according to the selected set of driving waveforms.

摘要翻译： 提供电泳显示器及其驱动方法。 电泳显示器包括显示面板，存储单元，定时控制器（TCON）。 显示面板具有多个子像素。 存储单元存储多组驱动波形，其中驱动波形组中的驱动波形的长度彼此不同。 TCON具有分析模块，耦合到显示面板和存储单元，并且接收具有多个显示数据的图像信号。 分析模块分析显示数据以获得分析结果。 TCON根据分析结果选择一组驱动波形，并根据所选择的一组驱动波形驱动子像素。

公开(公告)号：US20120001958A1

公开(公告)日：2012-01-05

申请号：US13172854

申请日：2011-06-30

申请人： Chun-Ting Liu ,  Hsu-Ping Tseng ,  Yao-Jen Hsieh ,  Chi-Mao Hung ,  Ying Hua Hsu

发明人： Chun-Ting Liu ,  Hsu-Ping Tseng ,  Yao-Jen Hsieh ,  Chi-Mao Hung ,  Ying Hua Hsu

IPC分类号： G09G5/10 ,  G09G3/34 ,  G09G5/00

CPC分类号： G09G3/344 ,  G09G2310/06 ,  G09G2360/16

摘要： An electrophoretic display and a driving method thereof are provided. The electrophoretic display includes a display panel, a storage unit, a timing controller (TCON). The display panel has a plurality of sub-pixels. The storage unit stores a plurality sets of driving waveforms, wherein the lengths of driving waveforms in the sets of driving waveforms are different from each other. The TCON has an analysis module, couples to the display panel and the storage unit, and receives an image signal having a plurality of display data. The analysis module analyzes the display data to obtain a analysis result. The TCON selects one of the sets of driving waveforms according to the analysis result, and drives the sub-pixels according to the selected set of driving waveforms.

摘要翻译： 提供电泳显示器及其驱动方法。 电泳显示器包括显示面板，存储单元，定时控制器（TCON）。 显示面板具有多个子像素。 存储单元存储多组驱动波形，其中驱动波形组中的驱动波形的长度彼此不同。 TCON具有分析模块，耦合到显示面板和存储单元，并且接收具有多个显示数据的图像信号。 分析模块分析显示数据以获得分析结果。 TCON根据分析结果选择一组驱动波形，并根据所选择的一组驱动波形驱动子像素。

公开(公告)号：US20120001957A1

公开(公告)日：2012-01-05

申请号：US13172844

申请日：2011-06-30

申请人： Chun-Ting Liu ,  Hsu-Ping Tseng ,  Chi-Mao Hung ,  Wei-Min Sun ,  Wen-Pin Chiu ,  Pei-Lin Tien ,  Yan-Liang Wu ,  Ying Hua Hsu

发明人： Chun-Ting Liu ,  Hsu-Ping Tseng ,  Chi-Mao Hung ,  Wei-Min Sun ,  Wen-Pin Chiu ,  Pei-Lin Tien ,  Yan-Liang Wu ,  Ying Hua Hsu

IPC分类号： G09G5/10 ,  G09G3/34

CPC分类号： G09G3/344 ,  G09G3/2044 ,  G09G2360/16

摘要： An electrophoretic display and a driving method thereof are provided. The electrophoretic display includes a display panel, a storage unit and a timing controller. The display panel has a plurality of sub pixels. The storage unit stores a plurality of sets of multiple-grayscale driving waveforms, in which the driving voltage scales of driving waveforms corresponding to a same grayscale in the sets of multiple-grayscale driving waveforms are different from each other. The timing controller is coupled to the storage unit and the display panel and receives an image signal, and when the image signal transmits a multiple-grayscale frame, the timing controller sequentially adopts the sets of multiple-grayscale driving waveforms to drive the sub pixels.

摘要翻译： 提供电泳显示器及其驱动方法。 电泳显示器包括显示面板，存储单元和定时控制器。 显示面板具有多个子像素。 存储单元存储多组多灰阶驱动波形，其中在多个灰度级驱动波形的集合中对应于相同灰度的驱动波形的驱动电压标度彼此不同。 定时控制器耦合到存储单元和显示面板并接收图像信号，并且当图像信号发送多灰阶帧时，定时控制器顺序地采用多个灰阶驱动波形的集合来驱动子像素。

公开(公告)号：US07595249B2

公开(公告)日：2009-09-29

申请号：US12286239

申请日：2008-09-29

申请人： Young-Kai Chen ,  Lay-Lay Chua ,  Vincent Etienne Houtsma ,  Rose Fasano Kopf ,  Andreas Leven ,  Chun-Ting Liu ,  Wei-Jer Sung ,  Yang Yang

发明人： Young-Kai Chen ,  Lay-Lay Chua ,  Vincent Etienne Houtsma ,  Rose Fasano Kopf ,  Andreas Leven ,  Chun-Ting Liu ,  Wei-Jer Sung ,  Yang Yang

IPC分类号： H01L21/331 ,  H01L21/8222

CPC分类号： H01L29/66318 ,  H01L29/7371

摘要： A method for fabricating a bipolar transistor includes forming a vertical sequence of semiconductor layers, forming an implant mask on the last formed semiconductor layer, and implanting dopant ions into a portion of one or more of the semiconductor layers. The sequence of semiconductor layers includes a collector layer, a base layer that is in contact with the collector layer, and an emitter layer that is in contact with the base layer. The implanting uses a process in which the implant mask stops dopant ions from penetrating into a portion of the sequence of layers.

摘要翻译： 一种用于制造双极晶体管的方法，包括形成垂直的半导体层序列，在最后形成的半导体层上形成注入掩模，以及将掺杂离子注入到一个或多个半导体层的一部分中。 半导体层的序列包括集电极层，与集电极层接触的基极层和与基极层接触的发射极层。 植入使用其中植入掩模阻止掺杂剂离子渗入层序列的一部分的过程。

公开(公告)号：US06794694B2

公开(公告)日：2004-09-21

申请号：US09742314

申请日：2000-12-21

申请人： Philip W Diodato ,  Chun-Ting Liu ,  Ruichen Liu

发明人： Philip W Diodato ,  Chun-Ting Liu ,  Ruichen Liu

IPC分类号： H01L2976

CPC分类号： H01L27/10852 ,  H01L21/76838 ,  H01L23/5223 ,  H01L27/10894 ,  H01L28/55 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit includes a semiconductor substrate with semiconductor devices formed therein and thereon, a first wiring layer located over the substrate, a second wiring layer located on the first wiring layer, and a capacitor. The capacitor has metal-based charge-storage electrodes that extend through the second wiring layer and at least part of the first wiring layer. The wiring layers have interconnect wire embedded therein.

摘要翻译： 集成电路包括其上形成有半导体器件的半导体衬底及其上，位于衬底上的第一布线层，位于第一布线层上的第二布线层和电容器。 电容器具有延伸穿过第二布线层和至少部分第一布线层的金属基电荷存储电极。 布线层具有嵌入其中的互连线。

公开(公告)号：US6054722A

公开(公告)日：2000-04-25

申请号：US848141

申请日：1997-04-28

申请人： Kua-Hua Lee ,  Chun-Ting Liu

发明人： Kua-Hua Lee ,  Chun-Ting Liu

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L27/11 ,  H01L29/786 ,  H01L27/108 ,  H01L27/01

CPC分类号： H01L27/1108 ,  Y10S257/903 ,  Y10S257/904

摘要： A complementary device consisting of a PMOS TFT transistor and an NMOS FET transistor uses a conducting layer to shunt drain regions of the transistors to eliminate any detrimental diode or p-n junction effects. The use of the conducting layer significantly improves the current drive capabilities of the PMOS TFT when the complementary device is used to design SRAM cells with NMOS pull-down transistors.

摘要翻译： 由PMOS TFT晶体管和NMOS FET晶体管构成的互补器件使用导电层来分流晶体管的漏极区以消除任何有害的二极管或p-n结效应。 当使用互补器件来设计具有NMOS下拉晶体管的SRAM单元时，使用导电层可显着提高PMOS TFT的电流驱动能力。

公开(公告)号：US5956618A

公开(公告)日：1999-09-21

申请号：US828155

申请日：1997-03-27

申请人： Chun-Ting Liu ,  Kuo-Hua Lee ,  Ruichen Liu

发明人： Chun-Ting Liu ,  Kuo-Hua Lee ,  Ruichen Liu

IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L21/027 ,  H01L21/304

CPC分类号： H01L21/76838 ,  Y10S438/942

摘要： A method for fabricating a multi-level integrated circuit is disclosed which utilizes a grid pattern from which portions corresponding to the metal layer are selectively removed to form a mask which is subsequently used to deposit dummy features in the open areas between metal lines, thereby to allow the deposition of a substantially planar dielectric surface over the metal layers and dummy features.

摘要翻译： 公开了一种用于制造多电平集成电路的方法，其利用网格图案，从其中选择性地去除与金属层相对应的部分以形成掩模，其随后用于在金属线之间的开放区域中沉积虚拟特征，从而 允许在金属层和虚拟特征上沉积基本上平面的电介质表面。

公开(公告)号：US5656822A

公开(公告)日：1997-08-12

申请号：US520087

申请日：1995-08-28

申请人： Kuo-Hua Lee ,  Chun-Ting Liu

发明人： Kuo-Hua Lee ,  Chun-Ting Liu

IPC分类号： H01L29/423 ,  H01L29/786 ,  H01L29/04 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/20

CPC分类号： H01L29/78696 ,  H01L29/42384

摘要： The longitudinal edges of the overlying channel layer of a thin-film transistor are substantially aligned with the longitudinal edges of the underlying polysilicon gate layer. As a result of this line-on-line arrangement of the channel and gate layers, integration area is minimized so that optimum integration density is achieved. Source-to-drain on current is increased as the result of the increased channel width gained from the sidewall section of the polysilicon gate, which may occur as a result of the permissible lateral extension of the body (channel) layer over one longitudinal edge of the channel gate layer due to a misalignment in lithography or processing delta.

摘要翻译： 薄膜晶体管的上覆通道层的纵向边缘基本上与下面的多晶硅栅极层的纵向边缘对准。 作为通道和栅极层的在线布置的结果，集成区域被最小化，从而实现最佳的集成密度。 由于从多晶硅栅极的侧壁部分增加的沟道宽度的结果，源极到漏极电流增加，这可能由于主体（沟道）层在一个纵向边缘上的允许的横向延伸 由于光刻或处理三角形中的未对准而导致的沟道栅极层。

公开(公告)号：US20050230784A1

公开(公告)日：2005-10-20

申请号：US10341777

申请日：2003-01-14

申请人： Yang Yang ,  Chun-Ting Liu ,  Rose Kopf ,  Chen-Jung Chen ,  Lay-Lay Chua

发明人： Yang Yang ,  Chun-Ting Liu ,  Rose Kopf ,  Chen-Jung Chen ,  Lay-Lay Chua

IPC分类号： G02B6/10 ,  G02B6/12 ,  G02B6/122 ,  G02B6/26 ,  H01L29/00 ,  H01L27/102

CPC分类号： G02B6/10 ,  G02B6/12004 ,  G02B6/1221 ,  G02B6/26 ,  G02B2006/12038 ,  G02B2006/12061 ,  G02B2006/12069 ,  G02B2006/12097 ,  G02B2006/12176 ,  G02B2006/12197

摘要： The present invention provides a method for adhering dielectric layers to metals, in particular inert metals, using an adhesive layer comprising silicon-rich silicon nitride. Good adhesion is achieved at temperatures of less than 300° C., thereby facilitating the fabrication of semiconductor structures containing II-VI and III-V semiconductors.

摘要翻译： 本发明提供一种使用包含富硅氮化硅的粘合剂层将电介质层粘附到金属，特别是惰性金属的方法。 在低于300℃的温度下实现良好的附着力，从而有助于制造含有II-VI和III-V半导体的半导体结构。

公开(公告)号：US20050156195A1

公开(公告)日：2005-07-21

申请号：US11079166

申请日：2005-03-14

申请人： Young-Kai Chen ,  Lay-Lay Chua ,  Vincent Houtsma ,  Rose Kopf ,  Andreas Leven ,  Chun-Ting Liu ,  Wei-Jer Sung ,  Yang Yang

发明人： Young-Kai Chen ,  Lay-Lay Chua ,  Vincent Houtsma ,  Rose Kopf ,  Andreas Leven ,  Chun-Ting Liu ,  Wei-Jer Sung ,  Yang Yang

IPC分类号： H01L21/331 ,  H01L29/737 ,  H01L29/739 ,  H01L31/0328 ,  H01L31/0336

CPC分类号： H01L29/66318 ,  H01L29/7371

摘要： A method for fabricating a bipolar transistor includes forming a vertical sequence of semiconductor layers, forming an implant mask on the last formed semiconductor layer, and implanting dopant ions into a portion of one or more of the semiconductor layers. The sequence of semiconductor layers includes a collector layer, a base layer that is in contact with the collector layer, and an emitter layer that is in contact with the base layer. The implanting uses a process in which the implant mask stops dopant ions from penetrating into a portion of the sequence of layers.