公开(公告)号：US6133136A

公开(公告)日：2000-10-17

申请号：US314003

申请日：1999-05-19

申请人： Daniel Charles Edelstein ,  Vincent McGahay ,  Henry A. Nye, III ,  Brian George Reid Ottey ,  William H. Price

发明人： Daniel Charles Edelstein ,  Vincent McGahay ,  Henry A. Nye, III ,  Brian George Reid Ottey ,  William H. Price

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L21/60 ,  H01L23/485 ,  H01L21/4763

CPC分类号： H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/13007 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L23/3192 ,  H01L2924/0001 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01052 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/3025

摘要： A structure comprising a layer of copper, a barrier layer, a layer of AlCu, and a pad-limiting layer, wherein the layer of AlCu and barrier layer are interposed between the layer of copper and pad-limiting layer.

摘要翻译： 包括铜层，阻挡层，AlCu层和焊盘限制层的结构，其中AlCu层和阻挡层插入在铜层和焊盘限制层之间。

公开(公告)号：US06486557B1

公开(公告)日：2002-11-26

申请号：US09515110

申请日：2000-02-29

申请人： Charles R. Davis ,  Daniel Charles Edelstein ,  John C. Hay ,  Jeffrey C. Hedrick ,  Christopher Jahnes ,  Vincent McGahay ,  Henry A. Nye, III

发明人： Charles R. Davis ,  Daniel Charles Edelstein ,  John C. Hay ,  Jeffrey C. Hedrick ,  Christopher Jahnes ,  Vincent McGahay ,  Henry A. Nye, III

IPC分类号： H01L2348

CPC分类号： H01L21/76808 ,  H01L21/76835 ,  H01L23/5222 ,  H01L23/53228 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A multi-level, coplanar copper damascene interconnect structure on an integrated circuit chip includes a first planar interconnect layer on an integrated circuit substrate and having plural line conductors separated by a dielectric material having a relatively low dielectric constant and a relatively low elastic modulus. A second planar interconnect layer on the first planar interconnect layer comprises a dielectric film having an elastic modulus higher than in the first planar interconnect layer and conductive vias therethrough. The vias are selectively in contact with the line conductors. A third planar interconnect layer on the second planar interconnect layer has plural line conductors separated by the dielectric material and selectively in contact with the vias.

摘要翻译： 集成电路芯片上的多层共面铜镶嵌互连结构包括在集成电路基板上的第一平面互连层，并且具有由具有相对较低的介电常数和相对低的弹性模量的介电材料隔开的多个线导体。 第一平面互连层上的第二平面互连层包括具有高于第一平面互连层的弹性模量和通过其的导电通孔的电介质膜。 通孔选择性地与线路导体接触。 第二平面互连层上的第三平面互连层具有被电介质材料隔开并选择性地与通孔接触的多个线导体。

公开(公告)号：US20080118717A1

公开(公告)日：2008-05-22

申请号：US12018640

申请日：2008-01-23

申请人： Son Nguyen ,  Michael Lane ,  Stephen Gates ,  Xiao Liu ,  Vincent McGahay ,  Sanjay Mehta ,  Thomas Shaw

发明人： Son Nguyen ,  Michael Lane ,  Stephen Gates ,  Xiao Liu ,  Vincent McGahay ,  Sanjay Mehta ,  Thomas Shaw

IPC分类号： B32B3/00

CPC分类号： H01L21/3148 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/3122 ,  H01L21/76807 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76832 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10T428/24802 ,  H01L2924/00

摘要： The present invention provides a hardmask that is located on a surface of a low k dielectric material having at least one conductive feature embedded therein. The hardmask includes a lower region of a hermetic oxide material located adjacent to the low k dielectric material and an upper region comprising atoms of Si, C and H located above the hermetic oxide material. The present invention also provides a method of fabricating the inventive hardmask as well as a method to form an interconnect structure containing the same.

公开(公告)号：US20070158851A1

公开(公告)日：2007-07-12

申请号：US11306825

申请日：2006-01-12

申请人： Kaushik Chanda ,  James Demarest ,  Ronald Filippi ,  Roy Iggulden ,  Edward Kiewra ,  Vincent McGahay ,  Ping-Chuan Wang ,  Yun-Yu Wang

发明人： Kaushik Chanda ,  James Demarest ,  Ronald Filippi ,  Roy Iggulden ,  Edward Kiewra ,  Vincent McGahay ,  Ping-Chuan Wang ,  Yun-Yu Wang

IPC分类号： H01L21/4763 ,  H01L23/48

CPC分类号： H01L23/53238 ,  H01L21/76846 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

摘要： In the back end of an integrated circuit employing dual-damascene interconnects, the interconnect members have a first non-conformal liner that has a thicker portion at the top of the trench level of the interconnect; and a conformal second liner that combines with the first liner to block diffusion of the metal fill material.

摘要翻译： 在采用双镶嵌互连的集成电路的后端中，互连构件具有第一非保形衬套，其在互连的沟槽级的顶部具有较厚的部分; 以及与第一衬垫结合以阻挡金属填充材料的扩散的共形第二衬垫。

公开(公告)号：US20060027842A1

公开(公告)日：2006-02-09

申请号：US11248719

申请日：2005-10-12

申请人： Ronald Filippi ,  Lynne Gignac ,  Vincent McGahay ,  Conal Murray ,  Hazara Rathore ,  Thomas Shaw ,  Ping-Chuan Wang

发明人： Ronald Filippi ,  Lynne Gignac ,  Vincent McGahay ,  Conal Murray ,  Hazara Rathore ,  Thomas Shaw ,  Ping-Chuan Wang

IPC分类号： H01L29/76

CPC分类号： G01R31/2881

摘要： A device, system and method for evaluating reliability of a semiconductor chip are disclosed. Strain is determined at a location of interest in a structure. Failures are evaluated in a plurality of the structures after stress cycling to determine a strain threshold with respect to a feature characteristic. Structures on a chip or chips are evaluated based on the feature characteristic to predict reliability based on the strain threshold and the feature characteristic. Predictions and design changes may be made based on the results.

公开(公告)号：US20060024961A1

公开(公告)日：2006-02-02

申请号：US10710706

申请日：2004-07-29

申请人： Matthew Angyal ,  Peter Biolsi ,  Lawrence Clevenger ,  Habib Hichri ,  Bernd Kastenmeier ,  Michael Lane ,  Jeffrey Marino ,  Vincent McGahay ,  Theodorus Standaert

发明人： Matthew Angyal ,  Peter Biolsi ,  Lawrence Clevenger ,  Habib Hichri ,  Bernd Kastenmeier ,  Michael Lane ,  Jeffrey Marino ,  Vincent McGahay ,  Theodorus Standaert

IPC分类号： H01L21/4763

CPC分类号： H01L21/76826 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76844

摘要： Methods for sealing an organic ILD layer and a metal layer after an etching step. The method includes etching through an ILD layer and leaving a remaining portion of an underlying metal layer cap, maintaining the device in an inert gas, and depositing at least a portion of a liner into the opening to seal the ILD layer and the metal layer. Subsequent processing may include formation of a via by etching through the portion of the liner and the remaining portion of the cap layer, and depositing a metal.

摘要翻译： 在蚀刻步骤之后密封有机ILD层和金属层的方法。 该方法包括蚀刻穿过ILD层并留下下面的金属层帽的剩余部分，将该装置保持在惰性气体中，并将​​衬垫的至少一部分沉积到开口中以密封ILD层和金属层。 随后的处理可以包括通过蚀刻穿过衬套的一部分和盖层的剩余部分以及沉积金属来形成通孔。

公开(公告)号：US20060190846A1

公开(公告)日：2006-08-24

申请号：US11403332

申请日：2006-04-13

申请人： Habib Hichri ,  Xiao Liu ,  Vincent McGahay ,  Conal Murray ,  Jawahar Nayak ,  Thomas Shaw

发明人： Habib Hichri ,  Xiao Liu ,  Vincent McGahay ,  Conal Murray ,  Jawahar Nayak ,  Thomas Shaw

IPC分类号： G06F17/50

CPC分类号： H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： Stacked via pillars, such as metal via pillars, are provided at different and designated locations in IC chips to support the chip structure during processing and any related processing stresses such as thermal and mechanical stresses. These stacked via pillars connect and extend from a base substrate of the strip to a top oxide cap of the chip. The primary purpose of the stacked via pillars is to hold the chip structure together to accommodate any radial deformations and also to relieve any stress, thermal and/or mechanical, build-tip during processing or reliability testing. The stacked via pillars are generally not electrically connected to any active lines or vias, however in some embodiments the stacked via pillars can provide an additional function of providing an electrical connection in the chip.

摘要翻译： 通过支柱堆叠，例如金属通孔柱，在IC芯片的不同和指定位置处提供，以在加工过程中支持芯片结构以及任何相关的加工应力，例如热和机械应力。 这些堆叠的通孔柱从条带的基底衬底连接并延伸到芯片的顶部氧化物盖。 堆叠的通孔柱的主要目的是将芯片结构保持在一起以适应任何径向变形，并且还可以在处理或可靠性测试期间缓解任何应力，热和/或机械构造尖端。 堆叠的通孔柱通常不电连接到任何有源线或通孔，但是在一些实施例中，堆叠的通孔柱可以提供在芯片中提供电连接的附加功能。

公开(公告)号：US20050208781A1

公开(公告)日：2005-09-22

申请号：US10708735

申请日：2004-03-22

申请人： John Fitzsimmons ,  Michael Lane ,  Vincent McGahay ,  Thomas Shaw ,  Anthony Stamper

发明人： John Fitzsimmons ,  Michael Lane ,  Vincent McGahay ,  Thomas Shaw ,  Anthony Stamper

IPC分类号： B05D1/02 ,  H01L21/78 ,  H01L23/00

CPC分类号： H01L23/562 ,  H01L21/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming and the integrated circuit device structure formed having vertical interfaces adjacent an existing crack stop around a perimeter of a chip, whereby the vertical interface controls cracks generated during side processing of the device such as dicing, and in service from penetrating the crack stop. The vertical interface is comprised of a material that prevents cracks from damaging the crack stop by deflecting cracks away from penetrating the crack stop, or by absorbing the generated crack energies. Alternatively, the vertical interface may be a material that allows advancing cracks to lose enough energy such that they become incapable of penetrating the crack stop. The present vertical interfaces can be implemented in a number of ways such as, vertical spacers of release material, vertical trenches of release material or vertical channels of the release material.

摘要翻译： 形成方法和集成电路器件结构形成，具有与现有裂纹相邻的垂直接口围绕芯片的周边，由此垂直接口控制器件的侧面处理期间产生的裂纹，例如切割，并且在穿透裂纹停止 。 垂直界面由防止裂纹破坏裂纹的材料组成，通过使裂纹偏离穿透裂缝，或通过吸收所产生的裂纹能量来防止裂纹破裂。 或者，垂直界面可以是允许前进裂纹失去足够的能量使得它们不能穿透裂缝停止的材料。 现有的垂直接口可以以多种方式实现，例如释放材料的垂直间隔物，释放材料的垂直沟槽或释放材料的垂直通道。

公开(公告)号：US20050186689A1

公开(公告)日：2005-08-25

申请号：US10783462

申请日：2004-02-20

申请人： Ronald Filippi ,  Jason Gill ,  Vincent McGahay ,  Paul McLaughlin ,  Conal Murray ,  Hazara Rathore ,  Thomas Shaw ,  Ping-Chuan Wang

发明人： Ronald Filippi ,  Jason Gill ,  Vincent McGahay ,  Paul McLaughlin ,  Conal Murray ,  Hazara Rathore ,  Thomas Shaw ,  Ping-Chuan Wang

IPC分类号： H01L21/66 ,  H01L23/544

CPC分类号： H01L22/34 ,  H01L22/32 ,  H01L23/5226 ,  H01L23/562 ,  H01L2924/0002 ,  H05K1/0268 ,  H05K1/0269 ,  H05K1/092 ,  Y10S438/927 ,  Y10T29/49004 ,  H01L2924/00

摘要： A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling.

摘要翻译： 用于评估通过制造工艺构建的半导体芯片结构的可靠性的装置和方法包括根据制造过程构建的测试结构。 测试结构热循环，测量结构的产量。 基于在热循环之前的产量性能来评估由制造工艺构建的半导体芯片结构的可靠性。

公开(公告)号：US20050118803A1

公开(公告)日：2005-06-02

申请号：US10726140

申请日：2003-12-02

申请人： Habib Hichri ,  Xiao Liu ,  Vincent McGahay ,  Conal Murray ,  Jawahar Nayak ,  Thomas Shaw

发明人： Habib Hichri ,  Xiao Liu ,  Vincent McGahay ,  Conal Murray ,  Jawahar Nayak ,  Thomas Shaw

IPC分类号： H01L21/4763 ,  H01L23/00 ,  H01L23/58

CPC分类号： H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： Stacked via pillars, such as metal via pillars, are provided at different and designated locations in IC chips to support the chip structure during processing and any related processing stresses such as thermal and mechanical stresses. These stacked via pillars connect and extend from a base substrate of the strip to a top oxide cap of the chip. The primary purpose of the stacked via pillars is to hold the chip structure together to accommodate any radial deformations and also to relieve any stress, thermal and/or mechanical, build-up during processing or reliability testing. The stacked via pillars are generally not electrically connected to any active lines or vias, however in some embodiments the stacked via pillars can provide an additional function of providing an electrical connection in the chip.

摘要翻译： 通过支柱堆叠，例如金属通孔柱，在IC芯片的不同和指定位置处提供，以在加工期间支撑芯片结构以及任何相关的加工应力，例如热和机械应力。 这些堆叠的通孔柱从条带的基底衬底连接并延伸到芯片的顶部氧化物盖。 堆叠的通孔柱的主要目的是将芯片结构保持在一起以适应任何径向变形，并且还可以在处理或可靠性测试期间缓解任何应力，热和/或机械的积累。 堆叠的通孔柱通常不电连接到任何有源线或通孔，但是在一些实施例中，堆叠的通孔柱可以提供在芯片中提供电连接的附加功能。