公开(公告)号：US06486557B1

公开(公告)日：2002-11-26

申请号：US09515110

申请日：2000-02-29

申请人： Charles R. Davis ,  Daniel Charles Edelstein ,  John C. Hay ,  Jeffrey C. Hedrick ,  Christopher Jahnes ,  Vincent McGahay ,  Henry A. Nye, III

发明人： Charles R. Davis ,  Daniel Charles Edelstein ,  John C. Hay ,  Jeffrey C. Hedrick ,  Christopher Jahnes ,  Vincent McGahay ,  Henry A. Nye, III

IPC分类号： H01L2348

CPC分类号： H01L21/76808 ,  H01L21/76835 ,  H01L23/5222 ,  H01L23/53228 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A multi-level, coplanar copper damascene interconnect structure on an integrated circuit chip includes a first planar interconnect layer on an integrated circuit substrate and having plural line conductors separated by a dielectric material having a relatively low dielectric constant and a relatively low elastic modulus. A second planar interconnect layer on the first planar interconnect layer comprises a dielectric film having an elastic modulus higher than in the first planar interconnect layer and conductive vias therethrough. The vias are selectively in contact with the line conductors. A third planar interconnect layer on the second planar interconnect layer has plural line conductors separated by the dielectric material and selectively in contact with the vias.

摘要翻译： 集成电路芯片上的多层共面铜镶嵌互连结构包括在集成电路基板上的第一平面互连层，并且具有由具有相对较低的介电常数和相对低的弹性模量的介电材料隔开的多个线导体。 第一平面互连层上的第二平面互连层包括具有高于第一平面互连层的弹性模量和通过其的导电通孔的电介质膜。 通孔选择性地与线路导体接触。 第二平面互连层上的第三平面互连层具有被电介质材料隔开并选择性地与通孔接触的多个线导体。

公开(公告)号：US6133136A

公开(公告)日：2000-10-17

申请号：US314003

申请日：1999-05-19

申请人： Daniel Charles Edelstein ,  Vincent McGahay ,  Henry A. Nye, III ,  Brian George Reid Ottey ,  William H. Price

发明人： Daniel Charles Edelstein ,  Vincent McGahay ,  Henry A. Nye, III ,  Brian George Reid Ottey ,  William H. Price

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L21/60 ,  H01L23/485 ,  H01L21/4763

CPC分类号： H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/13007 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L23/3192 ,  H01L2924/0001 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01052 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/3025

摘要： A structure comprising a layer of copper, a barrier layer, a layer of AlCu, and a pad-limiting layer, wherein the layer of AlCu and barrier layer are interposed between the layer of copper and pad-limiting layer.

摘要翻译： 包括铜层，阻挡层，AlCu层和焊盘限制层的结构，其中AlCu层和阻挡层插入在铜层和焊盘限制层之间。

公开(公告)号：US06531759B2

公开(公告)日：2003-03-11

申请号：US09777540

申请日：2001-02-06

申请人： Richard A. Wachnik ,  Henry A. Nye, III ,  Charles R. Davis ,  Theodore H. Zabel ,  Phillip J. Restle

发明人： Richard A. Wachnik ,  Henry A. Nye, III ,  Charles R. Davis ,  Theodore H. Zabel ,  Phillip J. Restle

IPC分类号： H01L23552

CPC分类号： H01L23/556 ,  H01L24/11 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025

摘要： An integrated circuit, comprising: a semiconductor substrate, a plurality of last metal conductors disposed above said substrate, a bottom metallic layer disposed on said last metal conductors, a top metallic layer, and an alpha absorber disposed between said bottom and top metallic layers, said alpha absorber consisting essentially of a high-purity metal which is an alpha-particle absorber. The metal is, for example, of Ta, W, Re, Os or Ir.

公开(公告)号：US06908841B2

公开(公告)日：2005-06-21

申请号：US10251453

申请日：2002-09-20

申请人： Lloyd G. Burrell ,  Douglas Kemerer ,  Henry A. Nye, III ,  Hans-Joachim Barth ,  Emmanuel F. Crabbe ,  David Anderson ,  Joseph Chan

发明人： Lloyd G. Burrell ,  Douglas Kemerer ,  Henry A. Nye, III ,  Hans-Joachim Barth ,  Emmanuel F. Crabbe ,  David Anderson ,  Joseph Chan

IPC分类号： H01L21/60 ,  H01L23/485 ,  H01L21/44

CPC分类号： H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05546 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/13099 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00

摘要： A semiconductor device (200) having support structures (218, 226, 236) beneath wirebond regions (214) of contact pads (204) and a method of forming same. Low modulus dielectric layers (216, 222, 232) are disposed over a workpiece (212). Support structures (218, 226, 236) are formed in the low modulus dielectric layers (216, 222, 232), and support vias (224, 234) are formed between the support structures (218, 226, 236). A high modulus dielectric film (220, 230) is disposed between each low modulus dielectric layer (216, 222, 232), and a high modulus dielectric layer (256) is disposed over the top low modulus dielectric layer (232). Contact pads (204) are formed in the high modulus dielectric layer (256). Each support via (234) within the low modulus dielectric layer (232) resides directly above a support via (224) in the underlying low modulus dielectric layer (222), to form a plurality of via support stacks within the low modulus dielectric layers (216, 222, 232).

摘要翻译： 一种在接触焊盘（204）的引线键合区域（214）下方具有支撑结构（218,226,236）的半导体器件（200）及其形成方法。 低模量介电层（216,222,232）设置在工件（212）上方。 支撑结构（218,226,236）形成在低模量电介质层（216,222,232）中，并且支撑通孔（224,234）形成在支撑结构（218,226,236）之间。 高模量介电膜（220,230）设置在每个低模量介电层（216,222,232）之间，并且高模量介电层（256）设置在顶部低模量介电层（232）之上。 接触焊盘（204）形成在高模量介电层（256）中。 在低模量介电层（232）内的每个支撑件（234）直接位于下面的低模量介电层（222）中的支撑通孔（224）的上方，以在低模量介电层（222）内形成多个通孔支撑堆叠 216,222,232）。

公开(公告)号：US07517736B2

公开(公告)日：2009-04-14

申请号：US11307642

申请日：2006-02-15

申请人： Sanjay C. Mehta ,  Daniel C. Edelstein ,  John A. Fitzsimmons ,  Stephan Grunow ,  Henry A. Nye, III ,  David L. Rath

发明人： Sanjay C. Mehta ,  Daniel C. Edelstein ,  John A. Fitzsimmons ,  Stephan Grunow ,  Henry A. Nye, III ,  David L. Rath

IPC分类号： H01L21/82 ,  H01L21/4763

CPC分类号： H01L23/5226 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76844 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods are provided that enable the ability to use a less aggressive liner processes, while producing structures known to give a desired high stress migration and electro-migration reliability. The present invention circumvents the issue of sputter damage of low k (on the order of 3.2 or less) dielectric by creating the via “anchors” (interlocked and interpenetrated vias) through chemical means. This allows the elimination or significant reduction of the sputter-etching process used to create the via penetration (“drilling, gouging”) into the line below in the barrier/seed metallization step. The present invention achieves the above, while maintaining a reliable copper fill and device structure.

摘要翻译： 提供了使得能够使用较不积极的衬里工艺的能力，同时产生已知具有期望的高应力迁移和电迁移可靠性的结构。 本发明通过化学方法制造通孔“锚”（互锁和相互穿透的通孔）来规避低k（约3.2以下）电介质的溅射损伤问题。 这允许在阻挡/种子金属化步骤中消除或显着减少用于在下面的线中产生通孔穿透（“钻孔，气刨”）的溅射蚀刻工艺。 本发明实现上述，同时保持可靠的铜填充和装置结构。

公开(公告)号：US07273803B2

公开(公告)日：2007-09-25

申请号：US10724938

申请日：2003-12-01

申请人： Yu-Ting Cheng ,  Stefanie Ruth Chiras ,  Donald W. Henderson ,  Sung-Kwon Kang ,  Stephen James Kilpatrick ,  Henry A. Nye, III ,  Carlos J. Sambucetti ,  Da-Yuan Shih

发明人： Yu-Ting Cheng ,  Stefanie Ruth Chiras ,  Donald W. Henderson ,  Sung-Kwon Kang ,  Stephen James Kilpatrick ,  Henry A. Nye, III ,  Carlos J. Sambucetti ,  Da-Yuan Shih

IPC分类号： H01L21/44

CPC分类号： B32B15/01 ,  Y10T428/12528 ,  Y10T428/31681

摘要： A ball-limiting metallurgy includes a substrate, a barrier layer formed over the substrate, an adhesion layer formed over the barrier layer, a first solderable layer formed over the adhesion layer, a diffusion barrier layer formed over the adhesion layer, and a second solderable layer formed over the diffusion barrier layer.

摘要翻译： 限球冶金包括基板，在基板上形成的阻挡层，形成在阻挡层上的粘合层，形成在粘合层上的第一可焊层，形成在粘合层上的扩散阻挡层，以及第二可焊接 层形成在扩散阻挡层上。

公开(公告)号：US07923849B2

公开(公告)日：2011-04-12

申请号：US12113152

申请日：2008-04-30

申请人： Keith E. Fogel ,  Balaram Ghosal ,  Sung K. Kang ,  Stephen Kilpatrick ,  Paul A. Lauro ,  Henry A. Nye, III ,  Da-Yuan Shih ,  Donna S. Zupanski-Nielsen

发明人： Keith E. Fogel ,  Balaram Ghosal ,  Sung K. Kang ,  Stephen Kilpatrick ,  Paul A. Lauro ,  Henry A. Nye, III ,  Da-Yuan Shih ,  Donna S. Zupanski-Nielsen

IPC分类号： H01L21/00

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01055 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/00014

摘要： An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting composition including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components.

摘要翻译： 一种适于将微电子器件芯片倒装连接到封装的互连结构，包括二层，三层或四层限球组合物，包括粘附/反应阻挡层，并且具有与含锡的组分反应的焊料可湿性层 无铅焊料，使得可焊接层在焊接期间可以完全消耗，但在焊接期间与无铅焊料接触后，阻挡层保持不变。 一个或多个无铅焊料球选择性地位于焊料润湿层上，该无铅焊球包含锡作为主要成分和一种或多种合金成分。

公开(公告)号：US07037559B2

公开(公告)日：2006-05-02

申请号：US10426725

申请日：2003-05-01

申请人： Emanuel I. Cooper ,  Charles C. Goldsmith ,  Stephen Kilpatrick ,  Carmen M. Mojica ,  Henry A. Nye, III

发明人： Emanuel I. Cooper ,  Charles C. Goldsmith ,  Stephen Kilpatrick ,  Carmen M. Mojica ,  Henry A. Nye, III

IPC分类号： C25D3/54 ,  C22C12/00 ,  B05D1/18 ,  B05D7/17 ,  B05D7/21

CPC分类号： C23C2/04 ,  C23C2/08 ,  H05K3/3463 ,  H05K3/3473 ,  H05K2203/073 ,  Y10S428/936 ,  Y10T428/12493 ,  Y10T428/12528 ,  Y10T428/12708

摘要： A first metal is plated onto a substrate comprising a second metal by immersing the substrate into a bath comprising a compound of the first metal and an organic diluent. The second metal is more electropositive than the first metal. The organic diluent has a boiling point higher than a eutectic point in a phase diagram of the first and second metals. The bath is operated above the eutectic point but below the melting point of the second metal. For example, bismuth is immersion plated onto lead-free tin-based solder balls, and subsequently redistributed by fluxless reflow. Plated structures are also provided.

摘要翻译： 将第一金属通过将基底浸入包含第一金属和有机稀释剂的化合物的浴中而被镀在包含第二金属的基材上。 第二种金属比第一种金属更具有正电性。 在第一和第二金属的相图中，有机稀释剂的沸点高于共晶点。 该浴液在共晶点以上运行，但低于第二种金属的熔点。 例如，将铋浸渍在无铅锡基焊球上，随后通过无助焊回流重新分布。 还提供镀层结构。

公开(公告)号：US06261945B1

公开(公告)日：2001-07-17

申请号：US09501649

申请日：2000-02-10

申请人： Henry A. Nye, III ,  Vincent J. McGahay ,  Kurt A. Tallman

发明人： Henry A. Nye, III ,  Vincent J. McGahay ,  Kurt A. Tallman

IPC分类号： H01L214763

CPC分类号： H01L23/564 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A copper-interconnect, low-K dielectric integrated circuit has reduced corrosion of the interconnect when the crackstop next to the kerf is also used as the primacy barrier to oxygen diffusion through the dielectric, with corresponding elements of the crackstop being constructed simultaneously with the circuit interconnect elements; e.g. horizontal interconnect elements have a corresponding structure in the crackstop and vias between interconnect layers have corresponding structures in the crackstop.

摘要翻译： 当铜线互连低K电介质集成电路当切口旁边的裂缝也被用作通过电介质的氧扩散的主要障碍时，互连的腐蚀减弱，裂缝的相应元件与电路同时构成 互连元件; 例如 水平互连元件在断裂器中具有相应的结构，并且互连层之间的通孔在裂缝挡板中具有对应的结构。

公开(公告)号：US20120012642A1

公开(公告)日：2012-01-19

申请号：US13244576

申请日：2011-09-25

申请人： Keith E. Fogel ,  Balaram Ghosal ,  Sung K. Kang ,  Stephen Kilpatrick ,  Paul A. Lauro ,  Henry A. Nye, III ,  Da-Yuan Shih ,  Donna S. Zupanski-Nielsen

发明人： Keith E. Fogel ,  Balaram Ghosal ,  Sung K. Kang ,  Stephen Kilpatrick ,  Paul A. Lauro ,  Henry A. Nye, III ,  Da-Yuan Shih ,  Donna S. Zupanski-Nielsen

IPC分类号： B23K35/14 ,  B23K35/24

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01055 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/00014

摘要： An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting composition including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components. With a two-layer ball-limiting composition comprising an adhesion/reaction barrier layer, wherein the adhesion/reaction barrier layer serves both as an adhesion layer and a reaction barrier layer, the adhesion/reaction barrier layer can be comprised of a material selected from the group consisting of Zr and ZrN

摘要翻译： 一种适于将微电子器件芯片倒装连接到封装的互连结构，包括二层，三层或四层限球组合物，包括粘附/反应阻挡层，并且具有与含锡的组分反应的焊料可湿性层 无铅焊料，使得可焊接层在焊接期间可以完全消耗，但在焊接期间与无铅焊料接触后，阻挡层保持不变。 一个或多个无铅焊料球选择性地位于焊料润湿层上，该无铅焊球包含锡作为主要成分和一种或多种合金成分。 使用包含粘合/反应阻挡层的双层球限制组合物，其中粘附/反应阻挡层既用作粘合层又用作反应阻挡层，粘合/反应阻挡层可以由选自 由Zr和ZrN组成的组