公开(公告)号：US5107314A

公开(公告)日：1992-04-21

申请号：US670057

申请日：1991-03-15

申请人： Dawon Kahng ,  James D. Chadi

发明人： Dawon Kahng ,  James D. Chadi

IPC分类号： H01L27/092 ,  H01L29/51 ,  H01L29/78

CPC分类号： H01L29/513 ,  H01L27/092 ,  H01L29/517 ,  H01L29/78

摘要： A complementary MISFET uses gallium antimonide as the active material to utilize the high mobilities of both holes and electrons in such material. To avoid interfacial states at the gate interface, the gate insulator is an epitaxial composite layer formed by an appropriate superlattice of which the portion adjacent the channel region is free of intentional doping. The superlattice may comprise, for example, alternating layers of aluminum antimonide and aluminum arsenide or of aluminum antimonide and gallium arsenide.

摘要翻译： 互补MISFET使用锑化镓作为活性材料，以利用这种材料中空穴和电子的高迁移率。 为了避免栅极界面处的界面状态，栅极绝缘体是由合适的超晶格形成的外延复合层，其中邻近沟道区的部分没有有意掺杂。 超晶格可以包括例如交替的锑化铝和砷化铝或锑化铝和砷化镓的层。

公开(公告)号：US5286517A

公开(公告)日：1994-02-15

申请号：US927617

申请日：1992-08-07

申请人： Dawon Kahng ,  T. Yoshioka

发明人： Dawon Kahng ,  T. Yoshioka

IPC分类号： H05B33/18 ,  C09K11/77 ,  H05B33/12 ,  H05B33/14 ,  B05D5/12

CPC分类号： H05B33/14 ,  C09K11/773 ,  C09K11/7745

摘要： A flat panel display utilizes an array of eletroluminescent cells in which the active layer is of polycrystalline zinc sulfide that is the host for molecules of a ternary europium fluoride compound, advantageously lithium europium tetrafluoride. Each cell includes a pair of electrodes between which are a silicon dioxide barrier layer, sufficiently thin for electrons to tunnel therethrough, the active layer, and a capacitive dielectric layer. Other ternary europium tetrafluoride compounds are described for use as the active layer.

摘要翻译： 平板显示器使用电子发光单元阵列，其中活性层是多晶硫化锌，其是三元铕氟化物化合物的分子的主体，有利地是四氟化铕锂。 每个电池包括一对电极，在该对电极之间是二氧化硅阻挡层，其电子足够薄以穿透其中，有源层和电容电介质层。 其他三元铕四氟化物被描述为用作活性层。

公开(公告)号：US4214359A

公开(公告)日：1980-07-29

申请号：US967222

申请日：1978-12-07

申请人： Dawon Kahng

发明人： Dawon Kahng

IPC分类号： H01L21/033 ,  H01L21/762 ,  H01L29/78 ,  B01J17/00

CPC分类号： H01L21/033 ,  H01L21/76218 ,  H01L29/7834 ,  H01L29/7835 ,  Y10S148/117 ,  Y10S148/143

摘要： A method of making MOS devices, primarily in integrated circuit form, is disclosed. Device areas first are defined on a silicon semiconductor chip, typically by means of a silicon nitride pattern 13A-13B. This pattern then is used to locate impurity introductions and to define areas of semiconductor surface portion removal. The latter operation produces mesas 16-17 coincident with the device areas. By this combination of steps and silicon oxide regrowth 27 where silicon has been removed, well-defined conductivity type zones are formed under the silicon oxide portions to function as buried terminal zones 28, 29, 30 of MOS devices. In the sole critical mask registration step, one edge 38 of the gate electrode 31 is located relative to the boundary 39 of a buried terminal zone 28. Finally, the channel zone 34 and the other terminal zone 33 of an MOS transistor are emplaced by a self-alignment process, followed by a heating step which adjusts final device dimensions.

摘要翻译： 公开了一种以集成电路形式制造MOS器件的方法。 器件区域首先通过硅氮化物图案13A-13B定义在硅半导体芯片上。 然后，该图案用于定位杂质引入并限定半导体表面部分去除的区域。 后者的操作生成与设备区域一致的台式16-17。 通过这种步骤的组合和已经除去硅的二氧化硅再生长27，在氧化硅部分之下形成明确限定的导电类型区，以用作MOS器件的掩埋端子区28,29,30。 在唯一的临界掩模配准步骤中，栅极31的一个边缘38相对于掩埋端子区28的边界39定位。最后，MOS晶体管的沟道区34和另一个端区33被放置在 自对准过程，随后是调整最终器件尺寸的加热步骤。

公开(公告)号：US3964085A

公开(公告)日：1976-06-15

申请号：US605312

申请日：1975-08-18

申请人： Dawon Kahng ,  Ernest Edward La Bate ,  Martin Paul Lepselter ,  Joseph Raymond Ligenza

发明人： Dawon Kahng ,  Ernest Edward La Bate ,  Martin Paul Lepselter ,  Joseph Raymond Ligenza

IPC分类号： H01L21/8247 ,  G11C16/04 ,  H01L21/28 ,  H01L29/788 ,  H01L29/792 ,  H01L45/00 ,  H01L11/00 ,  H01L15/00 ,  B05D5/12

CPC分类号： H01L21/28282 ,  G11C16/0466 ,  H01L29/792 ,  H01L45/00

摘要： An SI.sub.1 I.sub.2 M (semiconductor-insulator.sub.1 -insulator.sub.2 -metal) memory structure, containing an impurity such as tungsten concentrated in a region including the interface ("I.sub.1 I.sub.2 ") region between the I.sub.1 and I.sub.2 region, is fabricated by depositing an oxide of the impurity, such as tungsten trioxide, on the then exposed, I.sub.1 layer prior to fabricating the I.sub.2 layer. The oxide of the impurity, such as tungsten trioxide, can be advantageously deposited by means of reactive evaporation.

公开(公告)号：US4460434A

公开(公告)日：1984-07-17

申请号：US487113

申请日：1983-04-26

申请人： Leo F. Johnson ,  Dawon Kahng

发明人： Leo F. Johnson ,  Dawon Kahng

IPC分类号： H01L21/263 ,  H01L21/3105 ,  H01L21/306 ,  B44C1/22 ,  C03C15/00 ,  C03C25/06

CPC分类号： H01L21/2633 ,  H01L21/31055

摘要： A method of planarizing a surface using ion beam milling at a non-normal angle of incidence that is useful in semiconductor device manufacture is described.

摘要翻译： 描述了一种使用离子束铣削以非正常入射角进行平面化的方法，其在半导体器件制造中是有用的。

公开(公告)号：US4271583A

公开(公告)日：1981-06-09

申请号：US128841

申请日：1980-03-10

申请人： Dawon Kahng ,  Theodore A. Shankoff

发明人： Dawon Kahng ,  Theodore A. Shankoff

IPC分类号： H01L21/76 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/316 ,  H01L21/32 ,  H01L21/762

CPC分类号： H01L21/32 ,  H01L21/7621 ,  Y10S148/117 ,  Y10S148/143 ,  Y10S438/944

摘要： In the fabrication of semiconductor integrated circuits which include recessed oxide isolation regions (29), formation of the undesired "bird's head" and "bird's beak" is avoided by reducing the rate of oxide growth from the sidewalls of isotropically etched recesses (22) while oxide is being grown from the bottoms of the recess regions. A silicon nitride mask (24) formed selectively on each of the sidewalls which has previously been coated with a thin silicon dioxide layer (23) reduces the rate of oxide growth therefrom, so that the oxidized recess regions have substantially planar surfaces after termination of the oxide growth.

摘要翻译： 在包括凹陷氧化物隔离区域（29）的半导体集成电路的制造中，通过从各向同性蚀刻的凹槽（22）的侧壁减小氧化物生长的速率来避免不期望的“鸟头”和“鸟嘴”的形成，同时 氧化物从凹陷区域的底部生长。 在先前已经涂覆有薄二氧化硅层（23）的每个侧壁上选择性地形成的氮化硅掩模（24）降低了氧化物从其生长的速率，使得氧化的凹陷区域在终止后具有基本平坦的表面 氧化物生长。

公开(公告)号：US4135289A

公开(公告)日：1979-01-23

申请号：US827105

申请日：1977-08-23

申请人： John R. Brews ,  Dawon Kahng

发明人： John R. Brews ,  Dawon Kahng

IPC分类号： H01L27/108 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L21/26

CPC分类号： H01L29/7838 ,  H01L29/0847 ,  H01L29/1033 ,  H01L27/108

摘要： A method for making a metal oxide semiconductor field effect transistor (MOSFET) is disclosed that results in a semiconductor device structure in which the source and drain regions are buried in the structure beneath a typically thick oxide and bulge out in the semiconductor underneath, but not contiguous with, the interface of a typically thin gate oxide with the semiconductor. This bulging of the buried drain, in an N-channel device, results in an electric field profile during operation which curves away from the interface in the neighborhood of the drain, thereby reducing deleterious transport of electrons from the channel to the gate oxide. The method can also be adapted for fabricating integrated memory cell arrays. This adaptation involves the implantation of one or more layers of dopant ions in the region of the semiconductor between the oxide interface and the bulging portion of the buried drain. The purpose of these layers is to control access of charge carriers to the surface and to control the charge storage properties of the surface region.

摘要翻译： 公开了一种用于制造金属氧化物半导体场效应晶体管（MOSFET）的方法，其导致半导体器件结构，其中源极和漏极区域被掩埋在通常厚的氧化物下面的结构中，并且在下面的半导体中突出，但不是 与通常具有半导体的薄栅极氧化物的界面相邻。 埋入漏极在N沟道器件中的这种凸起在操作期间导致电场分布曲线，其远离漏极附近的界面，从而减少电子从通道到栅极氧化物的有害传输。 该方法还可以适用于制造集成的存储单元阵列。 这种适应涉及在氧化物界面和掩埋漏极的凸出部分之间的半导体区域中注入一层或多层掺杂剂离子。 这些层的目的是控制电荷载体到表面的接近并控制表面区域的电荷存储性质。

公开(公告)号：US5198721A

公开(公告)日：1993-03-30

申请号：US690587

申请日：1991-02-24

申请人： Dawon Kahng ,  Toshihiro Yoshioka

发明人： Dawon Kahng ,  Toshihiro Yoshioka

IPC分类号： H05B33/18 ,  C09K11/77 ,  H05B33/12 ,  H05B33/14

CPC分类号： H05B33/14 ,  C09K11/773 ,  C09K11/7745

摘要： A flat panel display utilizes an array of eletroluminescent cells in which the active layer is of polycrystalline zinc sulfide that is the host for molecules of a ternary europium fluoride compound, advantageously lithium europium tetrafluoride. Each cell includes a pair of electrodes between which are a silicon dioxide barrier layer, sufficiently thin for electrons to tunnel therethrough, the active layer, and a capacitive dielectric layer. Other ternary europium tetrafluoride compounds are discribed for use as the active layer.

摘要翻译： 平板显示器使用电子发光单元阵列，其中活性层是多晶硫化锌，其是三元铕氟化物化合物的分子的主体，有利地是四氟化铕锂。 每个电池包括一对电极，在该对电极之间是二氧化硅阻挡层，其电子足够薄以穿透其中，有源层和电容电介质层。 其他三元铕四氟化物化合物被描述为用作活性层。

公开(公告)号：US4623912A

公开(公告)日：1986-11-18

申请号：US678569

申请日：1984-12-05

申请人： Chuan C. Chang ,  Dawon Kahng ,  Avid Kamgar ,  Louis C. Parrillo

发明人： Chuan C. Chang ,  Dawon Kahng ,  Avid Kamgar ,  Louis C. Parrillo

IPC分类号： H01L29/78 ,  H01L21/314 ,  H01L21/318 ,  H01L21/336 ,  H01L29/34

CPC分类号： H01L21/3144

摘要： A semiconductor integrated circuit includes a nitrided silicon dioxide layer typically 50 to 400 Angstroms thick located on a semiconductor medium. The nitrided layer is an original silicon dioxide layer that has been nitrided at its top surface, as by rapid (flash) heating in ammonia to about 1250 degrees C., in such a way that the resulting nitrided silicon dioxide layer is essentially a compound layer of silicon nitroxide on silicon dioxide in which the atomic concentration fraction of nitrogen falls from a value greater than 0.13 at the top surface of the compound layer to a value of about 0.13 within 30 Angstroms or less beneath the top surface, and advantageously to values of less than about 0.05 everywhere at distances greater than about 60 Angstroms or less beneath the top surface, except that the nitrogen fraction can rise to as much as about 0.10 in the layer at distances within about 20 Angstroms from the interface of the nitrided layer and the underlying semiconductor medium.

摘要翻译： 半导体集成电路包括位于半导体介质上的通常为50至400埃的氮化二氧化硅层。 氮化层是在其顶表面上被氮化的原始二氧化硅层，如通过在氨中快速（闪蒸）加热至约1250℃，使得所得氮化二氧化硅层基本上为化合物层 的氮氧化硅在二氧化硅上，其中氮的原子浓度分数从化合物层的顶表面处的大于0.13的值下降到在顶表面下30度以内的约0.13的值，并且有利地为 在顶表面下方距离大于约60埃或更小的位置处小于约0.05，不同之处在于氮层在距离氮化层和界面的界面约20埃内的层中可以上升至约0.10 底层半导体介质。

公开(公告)号：US4324038A

公开(公告)日：1982-04-13

申请号：US209755

申请日：1980-11-24

申请人： Chuan C. Chang ,  James A. Cooper, Jr. ,  Dawon Kahng ,  Shyam P. Murarka

发明人： Chuan C. Chang ,  James A. Cooper, Jr. ,  Dawon Kahng ,  Shyam P. Murarka

IPC分类号： H01L21/285 ,  H01L21/336 ,  H01L29/423 ,  H01L29/78 ,  H01L21/28

CPC分类号： H01L29/66621 ,  H01L21/28537 ,  H01L29/66643 ,  H01L29/7839

摘要： A method for making a MOSFET device (20) in a semiconductor body (10) includes the step of forming source and drain contact electrodes (12.1, 12.2) prior to growth of the gate oxide (10.3) and after formation of a high conductivity surface region (10.5). The exposed mutually opposing sidewall edges of each of the contact electrodes (12.1, 12.2) are coated with a sidewall silicon dioxide layer (15.1, 15.2), and the then exposed surface of the semiconductor body (10) between these sidewalls is etched to depth beneath the high conductivity surface region (10.5) in order to separate it into the source and drain regions (10.1, 10.2).Formation of the high conductivity region may be omitted by using Schottky barrier or impurity doped material for the contact electrodes (12.1, 12.2).

摘要翻译： 在半导体本体（10）中制造MOSFET器件（20）的方法包括在栅极氧化物（10.3）生长之前和形成高电导率表面之后形成源极和漏极接触电极（12.1,12.2）的步骤 地区（10.5）。 每个接触电极（12.1,12.2）的暴露的相互相对的侧壁边缘被涂覆有侧壁二氧化硅层（15.1,15.2），并且将这些侧壁之间的半导体本体（10）的暴露的表面蚀刻到深度 在高导电性表面区域（10.5）之下，以将其分离成源极和漏极区域（10.1,10.2）。 通过使用用于接触电极（12.1,12.2）的肖特基势垒或杂质掺杂材料，可以省略高导电性区域的形成。