公开(公告)号：US09064941B2

公开(公告)日：2015-06-23

申请号：US14601215

申请日：2015-01-20

申请人： Deok-young Jung ,  Pil-kyu Kang ,  Byung-lyul Park ,  Ji-soon Park ,  Seong-min Son ,  Jin-ho An ,  Ji-hwang Kim

发明人： Deok-young Jung ,  Pil-kyu Kang ,  Byung-lyul Park ,  Ji-soon Park ,  Seong-min Son ,  Jin-ho An ,  Ji-hwang Kim

IPC分类号： H01L21/4763 ,  H01L21/768 ,  H01L21/02 ,  H01L21/3105

CPC分类号： H01L21/76898 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/561 ,  H01L21/568 ,  H01L23/291 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L24/17 ,  H01L24/81 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16237 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/83005 ,  H01L2224/83102 ,  H01L2224/9202 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2224/16145 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00014

摘要： A semiconductor device includes a substrate including a first surface and a second surface opposite to each other, a through-via electrode extending through the substrate. The through-via electrode has an interconnection metal layer and a barrier metal layer surrounding a side surface of the interconnection metal layer. One end of the through-via electrode protrudes above the second surface. A spacer insulating layer may be provided on an outer sidewall of the through-via electrode. A through-via electrode pad is connected to the through-via electrode and extends on the spacer insulating layer substantially parallel to the second surface. A first silicon oxide layer and a silicon nitride layer are stacked on the second surface. A thickness of the first silicon oxide layer is greater than a thickness of the silicon nitride layer.

公开(公告)号：US08963336B2

公开(公告)日：2015-02-24

申请号：US14333509

申请日：2014-07-16

申请人： Deok-young Jung ,  Pil-kyu Kang ,  Byung-lyul Park ,  Ji-soon Park ,  Seong-min Son ,  Jin-ho An ,  Ji-hwang Kim

发明人： Deok-young Jung ,  Pil-kyu Kang ,  Byung-lyul Park ,  Ji-soon Park ,  Seong-min Son ,  Jin-ho An ,  Ji-hwang Kim

IPC分类号： H01L29/40 ,  H01L23/48

CPC分类号： H01L21/76898 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/561 ,  H01L21/568 ,  H01L23/291 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L24/17 ,  H01L24/81 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16237 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/83005 ,  H01L2224/83102 ,  H01L2224/9202 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2224/16145 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00014

摘要： A semiconductor device includes a substrate including a first surface and a second surface opposite to each other, a through-via electrode extending through the substrate. The through-via electrode has an interconnection metal layer and a barrier metal layer surrounding a side surface of the interconnection metal layer. One end of the through-via electrode protrudes above the second surface. A spacer insulating layer may be provided on an outer sidewall of the through-via electrode. A through-via electrode pad is connected to the through-via electrode and extends on the spacer insulating layer substantially parallel to the second surface. A first silicon oxide layer and a silicon nitride layer are stacked on the second surface. A thickness of the first silicon oxide layer is greater than a thickness of the silicon nitride layer.

摘要翻译： 半导体器件包括：基板，包括彼此相对的第一表面和第二表面;延伸穿过基板的通孔电极。 通孔电极具有互连金属层和围绕互连金属层的侧表面的阻挡金属层。 通孔电极的一端在第二表面上方突出。 间隔绝缘层可以设置在通孔电极的外侧壁上。 通孔电极焊盘连接到通孔电极并且在基本平行于第二表面的间隔绝缘层上延伸。 在第二表面上层叠第一氧化硅层和氮化硅层。 第一氧化硅层的厚度大于氮化硅层的厚度。

公开(公告)号：US20150130030A1

公开(公告)日：2015-05-14

申请号：US14541121

申请日：2014-11-13

申请人： Keum-hee Ma ,  Tae-je Cho ,  Ji-hwang Kim

发明人： Keum-hee Ma ,  Tae-je Cho ,  Ji-hwang Kim

IPC分类号： H01L25/10 ,  H01L23/48 ,  H01L23/31

CPC分类号： H01L25/105 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/562 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/15311 ,  H01L2924/00

摘要： A semiconductor package includes: a package base substrate; at least one first semiconductor chip disposed on the package base substrate; a first molding member disposed at a same level as the at least one first semiconductor chip and that does not cover an upper surface of the at least one first semiconductor chip; at least one second semiconductor chip stacked on the at least one first semiconductor chip so as to extend over the at least one first semiconductor chip and the first molding member, wherein the at least one first semiconductor chip and at least part of the first molding member are disposed between the package base substrate and the at least one second semiconductor chip; and a second molding member disposed at a same level as the at least one second semiconductor chip.

摘要翻译： 半导体封装包括：封装基底; 设置在所述封装基板上的至少一个第一半导体芯片; 第一模制构件，其设置在与所述至少一个第一半导体芯片相同的水平面处，并且不覆盖所述至少一个第一半导体芯片的上表面; 至少一个第二半导体芯片，堆叠在所述至少一个第一半导体芯片上，以便在所述至少一个第一半导体芯片和所述第一模制构件上延伸，其中所述至少一个第一半导体芯片和所述第一模制构件的至少一部分 设置在所述封装基底基板和所述至少一个第二半导体芯片之间; 以及设置在与所述至少一个第二半导体芯片相同水平面的第二模制构件。