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    Method and apparatus for polishing metal surfaces
    5.
    发明授权
    Method and apparatus for polishing metal surfaces 失效
    抛光金属表面的方法和设备

    公开(公告)号：US5759427A

    公开(公告)日：1998-06-02

    申请号：US704193

    申请日：1996-08-28

    申请人： Edward Cibulsky ,  Gerald Andrew Kiballa ,  Voya Rista Markovich ,  Gary Leigh Newman ,  John Francis Prikazsky ,  Michael Wozniak

    发明人： Edward Cibulsky ,  Gerald Andrew Kiballa ,  Voya Rista Markovich ,  Gary Leigh Newman ,  John Francis Prikazsky ,  Michael Wozniak

    IPC分类号： B24B7/06 ,  B24B37/04 ,  B24B41/047 ,  C23F1/08 ,  H05K3/06 ,  H05K3/26 ,  C23F1/02 ,  C23F1/44

    CPC分类号： B24B37/04 ,  B24B41/047 ,  B24B7/06 ,  C23F1/08 ,  H05K3/068 ,  H05K3/26 ,  H05K2203/025 ,  H05K2203/0346 ,  H05K2203/0353 ,  H05K2203/1509

    摘要： A technique for chemically planarizing an exposed surface of metal on a substrate to a pre-determined thickness is provided. The substrate has an exposed metal surface such as copper circuitry on a dielectric substrate which is to be planarized. Typically, this will be circuitization extending above a photoresist layer. A planarizing head is rotated against the substrate, with the planarizing head in contact with the metal surface on the substrate. A chemical etchant, essentially free of abrasive material, is continuously supplied to the interface between the metal surface and the planarizing head. The planarizing continues until a predetermined thickness of the metal has been reached. In circuit board manufacturing, this will form a surface co-planar with the photoresist. In some instances where significant height reduction is required, thus requiring significant metal removal, several passes of the substrate may be required or a device with multiple heads may be used. On all but the last pass or last head, the planarizing head may include a film of polyester impregnated with very fine grit, such as 15.mu. or less silicon carbide (SiC). However, on the final pass or head, a relatively hard surface roll, e.g., rubber, free of added grit, is used to ensure a planar surface free of gouges.

    摘要翻译： 提供了一种用于将基板上的金属的暴露表面化学平坦化至预定厚度的技术。 衬底具有暴露的金属表面，例如待平坦化的电介质衬底上的铜电路。 通常，这将是在光致抗蚀剂层之上延伸的电路。 平面化头相对于衬底旋转，平坦化头与衬底上的金属表面接触。 基本上不含研磨材料的化学蚀刻剂被连续供应到金属表面和平坦化头部之间的界面。 平面化继续，直到达到预定厚度的金属。 在电路板制造中，这将形成与光致抗蚀剂共面的表面。 在需要显着降低高度的一些情况下，因此需要显着的金属去除，可能需要多次通过基底，或者可以使用具有多个头部的装置。 除了最后一次或最后一个头部之外，平坦化头可以包括浸渍有非常细的砂砾的聚酯薄膜，例如15微米或更少的碳化硅（SiC）。 然而，在最后的通行或头部，使用相对硬的表面辊，例如没有添加砂砾的橡胶，以确保没有气刨的平面。

    Method of producing fine-line circuit boards using chemical polishing
    7.
    发明授权
    Method of producing fine-line circuit boards using chemical polishing 失效
    使用化学抛光生产细线电路板的方法

    公开(公告)号：US06547974B1

    公开(公告)日：2003-04-15

    申请号：US08495277

    申请日：1995-06-27

    申请人： Stanley Michael Albrechta ,  Christina Marie Boyko ,  Kathleen Lorraine Covert ,  Natalie Barbara Feilchenfeld ,  Voya Rista Markovich ,  William Earl Wilson ,  Michael Wozniak

    发明人： Stanley Michael Albrechta ,  Christina Marie Boyko ,  Kathleen Lorraine Covert ,  Natalie Barbara Feilchenfeld ,  Voya Rista Markovich ,  William Earl Wilson ,  Michael Wozniak

    IPC分类号： H01B1300

    CPC分类号： H05K3/22 ,  H05K3/06 ,  H05K3/062 ,  H05K3/108 ,  H05K2203/025 ,  H05K2203/0346 ,  H05K2203/0353 ,  H05K2203/0392 ,  H05K2203/1476

    摘要： A printed circuit board is produced by patterning a resist layer according to a circuit mask that defines desired circuit paths. The resist pattern layer is formed by removing the resist from the board in the desired circuit paths and a conductive material is plated onto the board in the resist voids defined by the circuit mask so that the height of the conductive material relative to the substrate equals or exceeds the height of the resist layer relative to the substrate. A low-reactive solution is applied over the conductive material and removes a surface portion of the conductive material. As the solution removes the conductive layer, it forms a film barrier and the solution composition changes, both of which substantially inhibits any further removal of the conductive material. Next, the film barrier is removed from the board allowing another film barrier to form stimulating the removal of further conductive material. The removal step is repeated until the conductive material is at a desired height relative to the height of the resist layer. The board is then finished using conventional circuit board fabrication techniques.

    摘要翻译： 通过根据限定所需电路路径的电路掩模图案化抗蚀剂层来制造印刷电路板。 抗蚀剂图案层通过在所需的电路路径中从基板上去除抗蚀剂而形成，并且导电材料被电镀在由电路掩模限定的抗蚀剂空隙中的基板上，使得导电材料相对于基板的高度等于或等于 超过抗蚀剂层相对于基底的高度。 将低反应性溶液施加在导电材料上并除去导电材料的表面部分。 当溶液去除导电层时，其形成膜阻挡层并且溶液组成发生变化，这两者基本上禁止任何进一步去除导电材料。 接下来，从板上去除膜屏障，允许另一个膜屏障形成刺激去除另外的导电材料。 重复去除步骤，直到导电材料相对于抗蚀剂层的高度处于期望的高度。 然后使用常规电路板制造技术完成电路板。

    Protection of a plated through hole from chemical attack
    8.
    发明授权
    Protection of a plated through hole from chemical attack 失效
    保护电镀通孔免受化学侵蚀

    公开(公告)号：US06537608B2

    公开(公告)日：2003-03-25

    申请号：US09752915

    申请日：2001-01-02

    申请人： Thomas R. Miller ,  Kristen A. Stauffer ,  Michael Wozniak

    发明人： Thomas R. Miller ,  Kristen A. Stauffer ,  Michael Wozniak

    IPC分类号： B05D512

    CPC分类号： H05K3/0094 ,  H05K3/385 ,  H05K2201/0959 ,  Y10S428/901 ,  Y10T428/24273 ,  Y10T428/24917 ,  Y10T428/249985

    摘要： A method of forming an electronic structure, including adhesively coupling a plated metallic layer (e.g. a copper layer) of a plated through hole (PTH) to holefill material (e.g., epoxy resin) distributed within the PTH. The adhesive coupling utilizes an adhesion promoter film on the plated metallic layer such that the adhesion promoter film is bonded to the resin. The adhesion promoter film may include a metallic oxide layer such as a layer containing cupric oxide and cuprous oxide, which could be formed from bathing a PTH plated with copper in a solution of sodium chlorite. The adhesion promoter film may alternatively include an organometallic layer such as a layer that includes a chemical complex of metal and an organic corrosion inhibitor. The organometallic layer could be formed from bathing the PTH in a bath of hydrogen peroxide, sulfuric acid, and the organic corrosion inhibitor.

    摘要翻译： 一种形成电子结构的方法，包括将电镀通孔（PTH）的电镀金属层（例如铜层）粘附到分布在PTH内的孔填充材料（例如环氧树脂）。 粘合剂偶联剂在镀金属层上使用粘合促进剂膜，使粘合促进剂膜与树脂结合。 粘合促进剂膜可以包括金属氧化物层，例如含有氧化铜和氧化亚铜的层，其可以通过在亚氯酸钠溶液中洗涤镀铜的PTH来形成。 粘合促进剂膜可以替代地包括有机金属层，例如包含金属和有机腐蚀抑制剂的化学络合物的层。 有机金属层可以通过在过氧化氢，硫酸和有机腐蚀抑制剂的浴中洗涤PTH而形成。

    Flexible strip structure for a parallel processor and method of fabricating the flexible strip
    9.
    发明授权
    Flexible strip structure for a parallel processor and method of fabricating the flexible strip 失效
    用于并行处理器的柔性带状结构和制造柔性条的方法

    公开(公告)号：US5489500A

    公开(公告)日：1996-02-06

    申请号：US97601

    申请日：1993-07-27

    申请人： John Andrejack ,  Natalie B. Feilchenfeld ,  David B. Stone ,  Paul G. Wilkin ,  Michael Wozniak

    发明人： John Andrejack ,  Natalie B. Feilchenfeld ,  David B. Stone ,  Paul G. Wilkin ,  Michael Wozniak

    IPC分类号： H05K1/00 ,  H05K3/00 ,  H05K3/46 ,  G03F7/26

    CPC分类号： H05K3/4635 ,  H05K3/462 ,  H05K3/4641 ,  H05K1/0393 ,  H05K2201/09318 ,  H05K2201/09536 ,  H05K3/0047 ,  H05K3/4623 ,  H05K3/4691

    摘要： Disclosed is a parallel processor packaging structure and a method for manufacturing the structure. The individual logic and memory elements are on printed circuit cards. These printed circuit boards and cards are, in turn, mounted on or connected to circuitized flexible substrates extending outwardly from a laminate of the circuitized, flexible substrates. Intercommunication is provided through a switch structure that is implemented in the laminate. The printed circuit cards are mounted on or connected to a plurality of circuitized flexible substrates, with one printed circuit card at each end of the circuitized flexible circuit. The circuitized flexible substrates connect the separate printed circuit boards and cards through the central laminate portion. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication. The planar circuitization, as data lines, address lines, and control lines of a logic chip or a memory chip are on the individual printed circuit boards and cards, which are connected through the circuitized flex, and communicate with other layers of flex through Z-axis circuitization (vias and through holes) in the laminate. The individual circuitized flexible strips are discrete subassemblies. These subassemblies are laminates of at least one internal power core, and at least one signal core, with a layer of dielectric between.

    摘要翻译： 公开了一种并行处理器封装结构和用于制造该结构的方法。 单独的逻辑和存储器元件在印刷电路卡上。 这些印刷电路板和卡依次安装在或连接到从电路化的柔性基板的层叠体向外延伸的电路化柔性基板上。 通过在层压板中实现的开关结构来提供互通。 印刷电路卡安装在或连接到多个电路化的柔性基板上，在电路化柔性电路的每一端具有一个印刷电路卡。 电路化的柔性基板通过中央层压体部分连接分开的印刷电路板和卡。 该层压部分为处理器间，存储器间，处理器间/存储器元件以及处理器到存储器总线互连和通信提供XY平面和Z轴互连。 作为逻辑芯片或存储器芯片的数据线，地址线和控制线的平面电路在通过电路化的柔性连接的各个印刷电路板和卡上，并且通过Z轴与其它柔性层通信， 轴向电路（通孔和通孔）。 各个电路化的柔性条是离散的子组件。 这些子组件是至少一个内部功率核心的层压板，以及至少一个信号芯，其间具有介电层。