公开(公告)号：US20120308241A1

公开(公告)日：2012-12-06

申请号：US13585942

申请日：2012-08-15

申请人： Egan G. Colgan ,  Sampath Purushothaman ,  Roy R. Yu

发明人： Egan G. Colgan ,  Sampath Purushothaman ,  Roy R. Yu

IPC分类号： H04B10/12

CPC分类号： H01L23/49816 ,  B23P11/00 ,  H01L21/78 ,  H01L2924/0002 ,  H05K1/11 ,  H05K1/14 ,  H05K7/00 ,  Y10T29/49826 ,  H01L2924/00

摘要： An enhanced 3D integration structure comprises a logic microprocessor chip bonded to a collection of vertically stacked memory slices and an optional set of outer vertical slices comprising optoelectronic devices. Such a device enables both high memory content in close proximity to the logic circuits and a high bandwidth for logic to memory communication. Additionally, the provision of optoelectronic devices in the outer slices of the vertical slice stack enables high bandwidth direct communication between logic processor chips on adjacent enhanced 3D modules mounted next to each other or on adjacent packaging substrates. A method to fabricate such structures comprises using a template assembly which enables wafer format processing of vertical slice stacks.

公开(公告)号：US20180340100A1

公开(公告)日：2018-11-29

申请号：US16004028

申请日：2018-06-08

申请人： James L. Hedrick ,  Robert Dennis Miller ,  Deborah Ann Neumayer ,  Sampath Purushothaman ,  Mary E. Rothwell ,  Willi Volksen ,  Roy R. Yu ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： James L. Hedrick ,  Robert Dennis Miller ,  Deborah Ann Neumayer ,  Sampath Purushothaman ,  Mary E. Rothwell ,  Willi Volksen ,  Roy R. Yu

IPC分类号： C09J9/00 ,  H01L25/00 ,  C09J11/04 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L21/683 ,  C09J183/04 ,  C09J179/08 ,  C09J179/04 ,  C09J11/06 ,  H01L25/065 ,  C08K7/24 ,  C08K5/548 ,  C08K5/5465 ,  C08K5/544 ,  C08K5/5425 ,  B82Y40/00 ,  B82Y30/00 ,  C08K3/04

摘要： The present invention related to CNT filled polymer composite system possessing a high thermal conductivity and high temperature stability so that it is a highly thermally conductive for use in 3D and 4D integration for joining device sub-laminate layers. The CNT/polymer composite also has a CTE close to that of Si, enabling a reduced wafer structural warping during high temperature processing cycling. The composition is tailored to be suitable for coating, curing and patterning by means conventionally known in the art.

公开(公告)号：US20170271207A9

公开(公告)日：2017-09-21

申请号：US13972396

申请日：2013-08-21

申请人： Sampath Purushothaman ,  Roy R. Yu

发明人： Sampath Purushothaman ,  Roy R. Yu

IPC分类号： H01L21/768 ,  H01L21/762 ,  H01L23/538

CPC分类号： H01L21/76897 ,  H01L21/76256 ,  H01L21/76898 ,  H01L23/5384 ,  H01L23/5389 ,  H01L25/0657 ,  H01L2224/11 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

摘要： A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer comprising a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer.

公开(公告)号：US20140024146A1

公开(公告)日：2014-01-23

申请号：US13565848

申请日：2012-08-03

申请人： Diego Anzola ,  Evan G. Colgan ,  Kevin K. Dezfulian ,  Daniel C. Edelstein ,  Mark C. H. Lamorey ,  Sampath Purushothaman ,  Thomas M. Shaw ,  Roy R. Yu

发明人： Diego Anzola ,  Evan G. Colgan ,  Kevin K. Dezfulian ,  Daniel C. Edelstein ,  Mark C. H. Lamorey ,  Sampath Purushothaman ,  Thomas M. Shaw ,  Roy R. Yu

IPC分类号： H01L21/768 ,  H01L21/50 ,  H01L21/66

CPC分类号： H01L23/585 ,  H01L23/562 ,  H01L25/0657 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2225/06551 ,  H01L2225/06565

摘要： A semiconductor structure is provided and includes a substrate having an edge surface and a device surface with a central area, a crack stop structure disposed on the device surface and a circuit structure including components disposed on the device surface in the central area and interconnects electrically coupled to the components. The interconnects are configured to extend from the central area to the edge surface while bridging over the crack stop structure.

公开(公告)号：US08492869B2

公开(公告)日：2013-07-23

申请号：US13571920

申请日：2012-08-10

申请人： Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer ,  Steven J. Koester ,  Fei Liu ,  Sampath Purushothaman ,  Albert M. Young ,  Roy R. Yu

发明人： Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer ,  Steven J. Koester ,  Fei Liu ,  Sampath Purushothaman ,  Albert M. Young ,  Roy R. Yu

IPC分类号： H01L21/50

CPC分类号： H01L25/50 ,  H01L21/6835 ,  H01L21/76898 ,  H01L21/8221 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/0557 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73153 ,  H01L2224/73253 ,  H01L2224/83121 ,  H01L2224/83895 ,  H01L2224/92242 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/37001 ,  H01L2224/80001 ,  H01L2924/014 ,  H01L2224/83 ,  H01L2224/11

摘要： A 3D integrated circuit structure is provided. The 3D integrated circuit structure includes an interface wafer including a first wiring layer, a first active circuitry layer including active circuitry, and a wafer including active circuitry. The first active circuitry layer is bonded face down to the interface wafer, and the wafer is bonded face down to the first active circuitry layer. The first active circuitry layer is lower-cost than the wafer.

摘要翻译： 提供了3D集成电路结构。 3D集成电路结构包括接口晶片，其包括第一布线层，包括有源电路的第一有源电路层和包括有源电路的晶片。 第一有源电路层面向下接合到接口晶片，并且晶片正面朝下地接合到第一有源电路层。 第一有源电路层比晶片成本低。

公开(公告)号：US08399336B2

公开(公告)日：2013-03-19

申请号：US12194211

申请日：2008-08-19

申请人： Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer ,  Steven J. Koester ,  Fei Liu ,  Sampath Purushothaman ,  Albert M. Young ,  Roy R. Yu

发明人： Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer ,  Steven J. Koester ,  Fei Liu ,  Sampath Purushothaman ,  Albert M. Young ,  Roy R. Yu

IPC分类号： H01L21/30

CPC分类号： H01L25/50 ,  H01L21/6835 ,  H01L21/76898 ,  H01L21/8221 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/0557 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73153 ,  H01L2224/73253 ,  H01L2224/83121 ,  H01L2224/83895 ,  H01L2224/92242 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/37001 ,  H01L2224/80001 ,  H01L2924/014 ,  H01L2224/83 ,  H01L2224/11

摘要： A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer that includes active circuitry is provided, and a first portion of the first active circuitry layer wafer is removed such that a second portion of the first active circuitry layer wafer remains. Another wafer that includes active circuitry is provided, and the other wafer is bonded to the second portion of the first active circuitry layer wafer. The first active circuitry layer wafer is lower-cost than the other wafer. Also provided are a tangible computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.

摘要翻译： 提供了一种用于制造3D集成电路结构的方法。 根据该方法，提供包括有源电路的第一有源电路层晶片，并且去除第一有源电路层晶片的第一部分，使得第一有源电路层晶片的第二部分保留。 提供了包括有源电路的另一个晶片，另一个晶片结合到第一有源电路层晶片的第二部分。 第一有源电路层晶片比另一个晶片低成本。 还提供了用用于制造3D集成电路结构的程序编码的有形计算机可读介质和3D集成电路结构。

公开(公告)号：US20120309127A1

公开(公告)日：2012-12-06

申请号：US13572037

申请日：2012-08-10

申请人： Mukta G. FAROOQ ,  Robert Hannon ,  Subramanian S. Iyer ,  Steven J. Koester ,  Fei Liu ,  Sampath Purushothaman ,  Albert M. Young ,  Roy R. Yu

发明人： Mukta G. FAROOQ ,  Robert Hannon ,  Subramanian S. Iyer ,  Steven J. Koester ,  Fei Liu ,  Sampath Purushothaman ,  Albert M. Young ,  Roy R. Yu

IPC分类号： H01L21/60

CPC分类号： H01L25/0657 ,  H01L21/6835 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05024 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05558 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/056 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73153 ,  H01L2224/73253 ,  H01L2224/83121 ,  H01L2224/83895 ,  H01L2224/92242 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/37001 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00014

摘要： A computer readable medium is provided that is encoded with a program comprising instructions for performing a method for fabricating a 3D integrated circuit structure. Provided are an interface wafer including a first wiring layer and through-silicon vias, and a first active circuitry layer wafer including active circuitry. The first active circuitry layer wafer is bonded to the interface wafer. Then, a first portion of the first active circuitry layer wafer is removed such that a second portion remains attached to the interface wafer. A stack structure including the interface wafer and the second portion of the first active circuitry layer wafer is bonded to a base wafer. Next, the interface wafer is thinned so as to form an interface layer, and metallizations coupled through the through-silicon vias in the interface layer to the first wiring layer are formed on the interface layer.

摘要翻译： 提供了一种计算机可读介质，其由包括用于执行制造3D集成电路结构的方法的指令的程序编码。 提供了包括第一布线层和穿硅通孔的接口晶片，以及包括有源电路的第一有源电路层晶片。 第一有源电路层晶片被结合到界面晶片。 然后，去除第一有源电路层晶片的第一部分，使得第二部分保持附着到界面晶片。 包括接口晶片和第一有源电路层晶片的第二部分的堆叠结构被结合到基底晶片。 接下来，将界面晶片减薄以形成界面层，并且在界面层上形成通过界面层中的穿硅通孔耦合到第一布线层的金属化。

公开(公告)号：US20120149173A1

公开(公告)日：2012-06-14

申请号：US13398481

申请日：2012-02-16

申请人： Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer ,  Steven J. Koester ,  Sampath Purushothaman ,  Roy R. Yu

发明人： Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer ,  Steven J. Koester ,  Sampath Purushothaman ,  Roy R. Yu

IPC分类号： H01L21/30

CPC分类号： H01L27/105 ,  H01L24/11 ,  H01L27/0688 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05024 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599

摘要： A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer is provided. The first active circuitry layer wafer comprises a P+ portion covered by a P− layer, and the P− layer includes active circuitry. The first active circuitry layer wafer is bonded face down to an interface wafer that includes a first wiring layer, and then the P+ portion of the first active circuitry layer wafer is selectively removed with respect to the P− layer of the first active circuitry layer wafer. Next, a wiring layer is fabricated on the backside of the P− layer. Also provided are a non-transitory computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.

摘要翻译： 提供了一种用于制造3D集成电路结构的方法。 根据该方法，提供第一有源电路层晶片。 第一有源电路层晶片包括由P层覆盖的P +部分，并且P层包括有源电路。 第一有源电路层晶片面向下接合到包括第一布线层的接口晶片，然后相对于第一有源电路层晶片的P层选择性地去除第一有源电路层晶片的P +部分 。 接下来，在P-层的背面上制造布线层。 还提供了编码有用于制造3D集成电路结构的程序的非暂时计算机可读介质，以及3D集成电路结构。

公开(公告)号：US10767084B2

公开(公告)日：2020-09-08

申请号：US16004028

申请日：2018-06-08

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  James L. Hedrick ,  Robert Dennis Miller ,  Deborah Ann Neumayer ,  Sampath Purushothaman ,  Mary E. Rothwell ,  Willi Volksen ,  Roy R. Yu

发明人： James L. Hedrick ,  Robert Dennis Miller ,  Deborah Ann Neumayer ,  Sampath Purushothaman ,  Mary E. Rothwell ,  Willi Volksen ,  Roy R. Yu

IPC分类号： C09J9/00 ,  B32B17/00 ,  C09J179/08 ,  C09J11/04 ,  H01L23/16 ,  B32B33/00 ,  C09J11/06 ,  C09J179/04 ,  C09J183/04 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/768 ,  H01L21/683 ,  H01L23/60 ,  H01L23/48 ,  B82Y30/00 ,  B82Y40/00 ,  C08K5/544 ,  C08K5/548 ,  C08K5/5425 ,  C08K5/5465 ,  C08K7/24 ,  C08K3/04

摘要： The present invention related to CNT filled polymer composite system possessing a high thermal conductivity and high temperature stability so that it is a highly thermally conductive for use in 3D and 4D integration for joining device sub-laminate layers. The CNT/polymer composite also has a CTE close to that of Si, enabling a reduced wafer structural warping during high temperature processing cycling. The composition is tailored to be suitable for coating, curing and patterning by means conventionally known in the art.

公开(公告)号：US20170166784A1

公开(公告)日：2017-06-15

申请号：US14967353

申请日：2015-12-13

申请人： James L. Hedrick ,  Robert Dennis Miller ,  Deborah Ann Neumayer ,  Sampath Purushothaman ,  Mary E. Rothwell ,  Willi Volksen ,  Roy R. Yu

发明人： James L. Hedrick ,  Robert Dennis Miller ,  Deborah Ann Neumayer ,  Sampath Purushothaman ,  Mary E. Rothwell ,  Willi Volksen ,  Roy R. Yu

IPC分类号： C09J9/00 ,  H01L25/00 ,  H01L23/00 ,  C09J183/04 ,  C09J11/06 ,  C09J179/08 ,  C09J179/04 ,  H01L25/065 ,  C09J11/04

CPC分类号： C09J9/00 ,  B82Y30/00 ,  B82Y40/00 ,  C08K3/041 ,  C08K5/5425 ,  C08K5/544 ,  C08K5/5465 ,  C08K5/548 ,  C08K7/24 ,  C08K2201/01 ,  C09J11/04 ,  C09J11/06 ,  C09J179/04 ,  C09J179/08 ,  C09J183/04 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68363 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/11831 ,  H01L2224/13147 ,  H01L2224/13184 ,  H01L2224/13562 ,  H01L2224/13565 ,  H01L2224/1369 ,  H01L2224/16147 ,  H01L2224/27444 ,  H01L2224/27452 ,  H01L2224/27612 ,  H01L2224/2929 ,  H01L2224/29393 ,  H01L2224/29499 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2224/81201 ,  H01L2224/81903 ,  H01L2224/83005 ,  H01L2224/83192 ,  H01L2224/83201 ,  H01L2224/8385 ,  H01L2224/83855 ,  H01L2224/83856 ,  H01L2224/83895 ,  H01L2224/9202 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2225/06544 ,  Y10S977/742 ,  Y10S977/833 ,  Y10S977/843 ,  H01L2924/01006 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/83

摘要： The present invention relates to CNT filled polymer composite system possessing a high thermal conductivity and high temperature stability so that it is a highly thermally conductive for use in 3D and 4D integration for joining device sub-laminate layers. The CNT/polymer composite also has a CTE close to that of Si, enabling a reduced wafer structural warping during high temperature processing cycling. The composition is tailored to be suitable for coating, curing and patterning by means conventionally known in the art.