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    Apparatus and method for rounded ONO formation in a flash memory device
    5.
    发明授权
    Apparatus and method for rounded ONO formation in a flash memory device 有权
    闪存装置中圆形ONO形成的装置和方法

    公开(公告)号：US09564331B2

    公开(公告)日：2017-02-07

    申请号：US13540373

    申请日：2012-07-02

    申请人： Shenqing Fang ,  Tung-Sheng Chen ,  Tim Thurgate ,  Di Li

    发明人： Shenqing Fang ,  Tung-Sheng Chen ,  Tim Thurgate ,  Di Li

    IPC分类号： H01L29/792 ,  H01L21/28 ,  H01L29/66 ,  H01L27/115 ,  H01L21/762

    CPC分类号： H01L21/28282 ,  H01L21/76224 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/792

    摘要： A method and apparatus for continuously rounded charge trapping layer formation in a flash memory device. The memory device includes a semiconductor layer, including a source/drain region. An isolation region is disposed adjacent to the source/drain region. A first insulator is disposed above the source/drain region. A charge trapping layer is disposed within the first insulator, wherein the charge trapping layer comprises a bulk portion and a first tip and a second tip on either side of said bulk portion, wherein said charge trapping layer extends beyond the width of the source/drain region. A second insulator is disposed above the charge trapping layer. A polysilicon gate structure is disposed above the second insulator, wherein a width of said control gate is wider than the width of said source/drain region.

    摘要翻译： 一种用于在闪速存储器件中连续成形的电荷俘获层形成的方法和装置。 存储器件包括包括源/漏区的半导体层。 隔离区域邻近源极/漏极区域设置。 第一绝缘体设置在源极/漏极区域的上方。 电荷捕获层设置在第一绝缘体内，其中电荷捕获层包括主体部分和在所述主体部分的任一侧上的第一尖端和第二尖端，其中所述电荷捕获层延伸超过源极/漏极的宽度 地区。 第二绝缘体设置在电荷捕获层上方。 多晶硅栅极结构设置在第二绝缘体上方，其中所述控制栅极的宽度比所述源极/漏极区域的宽度宽。

    Method of forming memory devices by performing halogen ion implantation and diffusion processes
    8.
    发明授权
    Method of forming memory devices by performing halogen ion implantation and diffusion processes 有权
    通过卤素离子注入和扩散工艺形成存储器件的方法

    公开(公告)号：US07824994B2

    公开(公告)日：2010-11-02

    申请号：US12271132

    申请日：2008-11-14

    申请人： Kirk Prall ,  Behnam Moradi ,  Seiichi Aritome ,  Di Li ,  Chris Larsen

    发明人： Kirk Prall ,  Behnam Moradi ,  Seiichi Aritome ,  Di Li ,  Chris Larsen

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66825 ,  H01L21/22 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/324 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/788

    摘要： Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.

    摘要翻译： 公开了一种使用卤素离子注入和扩散工艺形成存储器件的方法。 在一个说明性实施例中，该方法包括在半导体衬底上形成多个字线结构，每个字线结构包括栅极绝缘层，执行LDD离子注入工艺，以在字线之间的衬底中形成LDD掺杂区域 结构，执行卤素离子注入工艺，以将卤素原子植入到半导体衬底中的字线结构之间，以及执行至少一个退火工艺以使至少一些卤素原子扩散到相邻字的栅极绝缘层中 线结构。

    Method of Forming Memory Devices by Performing Halogen Ion Implantation and Diffusion Processes
    9.
    发明申请
    Method of Forming Memory Devices by Performing Halogen Ion Implantation and Diffusion Processes 有权
    通过执行卤素离子注入和扩散过程形成存储器件的方法

    公开(公告)号：US20090068812A1

    公开(公告)日：2009-03-12

    申请号：US12271132

    申请日：2008-11-14

    申请人： Kirk Prall ,  Behnam Moradi ,  Seiichi Aritome ,  Di Li ,  Chris Larsen

    发明人： Kirk Prall ,  Behnam Moradi ,  Seiichi Aritome ,  Di Li ,  Chris Larsen

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66825 ,  H01L21/22 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/324 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/788

    摘要： Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.

    摘要翻译： 公开了一种使用卤素离子注入和扩散工艺形成存储器件的方法。 在一个说明性实施例中，该方法包括在半导体衬底上形成多个字线结构，每个字线结构包括栅极绝缘层，执行LDD离子注入工艺，以在字线之间的衬底中形成LDD掺杂区域 结构，执行卤素离子注入工艺，以将卤素原子植入到半导体衬底中的字线结构之间，以及执行至少一个退火工艺，以使至少一些卤素原子扩散到相邻字的栅极绝缘层中 线结构。

    Non-volatile memory cells without diffusion junctions
    10.
    发明申请
    Non-volatile memory cells without diffusion junctions 审中-公开
    不具有扩散结的非易失性存储单元

    公开(公告)号：US20060278913A1

    公开(公告)日：2006-12-14

    申请号：US11147976

    申请日：2005-06-08

    申请人： Andrei Mihnea ,  Behnam Moradi ,  Paul Rudeck ,  Aritome Seiichi ,  Di Li

    发明人： Andrei Mihnea ,  Behnam Moradi ,  Paul Rudeck ,  Aritome Seiichi ,  Di Li

    IPC分类号： H01L29/788 ,  H01L21/336 ,  G11C16/04

    CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

    摘要： A plurality of memory cell stacks are formed over a substrate. The substrate does not have diffusion regions between each memory cell stack to link the memory cells. The cells are formed close enough such that the memory cells are linked serially by the electric fields generated by each floating gate in the channel regions. In one embodiment, an n-layer is implanted at the top of the substrate to increase conductivity between cells. The select transistors can be linked to the serial string by diffusion regions or by interaction of the electric fields between the select transistor channel and the memory cell channel.

    摘要翻译： 多个存储单元堆叠形成在衬底上。 衬底在每个存储单元堆之间不具有扩散区，以连接存储单元。 电池形成得足够接近，使得存储器单元由通道区域中的每个浮动栅极产生的电场串联连接。 在一个实施例中，在衬底的顶部注入n层以增加电池之间的导电性。 选择晶体管可以通过扩散区域或通过选择晶体管沟道和存储单元通道之间的电场的相互作用而连接到串行串。