公开(公告)号：US07232513B1

公开(公告)日：2007-06-19

申请号：US10879613

申请日：2004-06-29

申请人： Eric G. Webb ,  Jonathan D. Reid ,  John H. Sukamto ,  Yuichi Takada

发明人： Eric G. Webb ,  Jonathan D. Reid ,  John H. Sukamto ,  Yuichi Takada

IPC分类号： C25D3/38 ,  C25D5/02

CPC分类号： C25D3/38 ,  C25D5/04 ,  C25D5/18

摘要： An electroplating solution contains a wetting agent in addition to a suppressor and an accelerator. In some embodiments, the solution has a cloud point temperature greater than 35° C. to avoid precipitation of wetting agent or other solute out of the plating solution. In some embodiments, the wetting agent decreases the air-liquid surface tension of the electroplating solution to 60 dyne/cm2 or less to increase the wetting ability of the solution with a substrate surface. In some embodiments of a method for plating metal onto substrate surface, the electroplating solution has a measured contact angle with the substrate surface less than 60 degrees.

摘要翻译： 除了抑制剂和促进剂之外，电镀溶液还含有润湿剂。 在一些实施方案中，溶液的浊点温度大于35℃，以避免润湿剂或其它溶质从电镀溶液中沉淀出来。 在一些实施方案中，润湿剂将电镀溶液的空气 - 液体表面张力降低至60达因/厘米2或更小，以增加溶液与基底表面的润湿能力。 在用于将金属电镀到衬底表面上的方法的一些实施例中，电镀溶液具有与衬底表面的测量的接触角小于60度。

公开(公告)号：US06884335B2

公开(公告)日：2005-04-26

申请号：US10441607

申请日：2003-05-20

申请人： Eric G. Webb ,  Jonathan D. Reid ,  John H. Sukamto ,  Sesha Varadarajan ,  Margolita M. Pollack ,  Bryan L. Buckalew ,  Tariq Majid

发明人： Eric G. Webb ,  Jonathan D. Reid ,  John H. Sukamto ,  Sesha Varadarajan ,  Margolita M. Pollack ,  Bryan L. Buckalew ,  Tariq Majid

IPC分类号： C25D5/04 ,  C25D5/18 ,  C25D7/12 ,  H01L21/288

CPC分类号： C25D5/04 ,  C25D5/18 ,  C25D7/123 ,  C25D17/001 ,  H01L21/2885 ,  Y10S428/935 ,  Y10T428/12993

摘要： A negative bias is applied to an integrated circuit wafer immersed in an electrolytic plating solution to generate a DC current. After about ten percent to sixty percent of the final layer thickness has formed in a first plating time, biasing is interrupted during short pauses during a second plating time to generate substantially zero DC current. The pauses are from about 2 milliseconds to 5 seconds long, and typically about 10 milliseconds to 500 milliseconds. Generally, about 2 pauses to 100 pauses are used, and typically about 3 pauses to 15 pauses. Generally, the DC current density during the second plating time is greater than the DC current density during the initial plating time. Typically, the integrated circuit wafer is rotated during electroplating. Preferably, the wafer is rotated at a slower rotation rate during the second plating time than during the first plating time.

摘要翻译： 将负偏压施加到浸在电解电镀溶液中的集成电路晶片以产生DC电流。 在第一电镀时间中已经形成最终层厚度的约百分之十到百分之六十之后，在第二电镀时间期间的短暂停期间偏压中断，以产生基本为零的DC电流。 停顿时间为大约2毫秒到5秒，通常为大约10毫秒到500毫秒。 通常，使用约2次暂停至100次暂停，通常约3次暂停至15次停顿。 通常，第二电镀时间期间的直流电流密度大于初始电镀时间期间的直流电流密度。 通常，电镀期间集成电路晶片旋转。 优选地，在第二电镀时间期间，晶片以比第一电镀时间期间更慢的旋转速度旋转。

公开(公告)号：US08513124B1

公开(公告)日：2013-08-20

申请号：US12785205

申请日：2010-05-21

申请人： Thomas A. Ponnuswamy ,  John H. Sukamto ,  Jonathan D. Reid ,  Steven T. Mayer

发明人： Thomas A. Ponnuswamy ,  John H. Sukamto ,  Jonathan D. Reid ,  Steven T. Mayer

IPC分类号： H01L21/44

CPC分类号： H01L21/76873 ,  C25D3/38 ,  C25D5/18 ,  C25D5/50 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/76843 ,  H01L21/76864 ,  H01L2221/1089

摘要： Disclosed are methods of depositing a copper seed layer to be used for subsequent electroplating a bulk-layer of copper thereon. A copper seed layer may be deposited with different processes, including CVD, PVD, and electroplating. With electroplating methods for depositing a copper seed layer, disclosed are methods for depositing a copper alloy seed layer, methods for depositing a copper seed layer on the semi-noble metal layer with a non-corrosive electrolyte, methods of treating the semi-noble metal layer that the copper seed layer is deposited on, and methods for promoting a more uniform copper seed layer deposition across a semiconductor wafer.

摘要翻译： 公开了一种沉积铜籽晶层的方法，该铜籽晶层用于随后电镀铜的体层。 铜种子层可以以不同的工艺沉积，包括CVD，PVD和电镀。 利用用于沉积铜籽晶层的电镀方法，公开了用于沉积铜合金晶种层的方法，用非腐蚀性电解质在半贵金属层上沉积铜籽晶层的方法，处理半贵金属的方法 沉积铜籽晶层的层，以及用于促进越过半导体晶片的更均匀的铜籽晶层沉积的方法。

公开(公告)号：US08703615B1

公开(公告)日：2014-04-22

申请号：US13367710

申请日：2012-02-07

申请人： Thomas A. Ponnuswamy ,  John H. Sukamto ,  Jonathan D. Reid ,  Steven T. Mayer ,  Huanfeng Zhu

发明人： Thomas A. Ponnuswamy ,  John H. Sukamto ,  Jonathan D. Reid ,  Steven T. Mayer ,  Huanfeng Zhu

IPC分类号： H01L21/44

CPC分类号： H01L21/76873 ,  C25D3/38 ,  C25D5/18 ,  C25D5/50 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/76843 ,  H01L21/76864 ,  H01L2221/1089

摘要： Disclosed are methods of depositing and annealing a copper seed layer. A copper seed layer may be deposited on a ruthenium layer disposed on a surface of a wafer and on features in the wafer. The thickness of the ruthenium layer may be about 40 Angstroms or less. The copper seed layer may be annealed in a reducing atmosphere having an oxygen concentration of about 2 parts per million or less. Annealing the copper seed layer in a low-oxygen atmosphere may improve the properties of the copper seed layer.

摘要翻译： 公开了沉积和退火铜籽晶层的方法。 可以将铜籽晶层沉积在设置在晶片表面上的钌层和晶片中的特征上。 钌层的厚度可以为约40埃或更小。 铜种子层可以在氧浓度为约2ppm或更少的还原气氛中退火。 在低氧气氛中退火铜籽晶层可以改善铜籽晶层的性能。

公开(公告)号：US07442267B1

公开(公告)日：2008-10-28

申请号：US10999838

申请日：2004-11-29

申请人： Eric G. Webb ,  Jonathan D. Reid ,  Seyang Park ,  Johanes H. Sukamto

发明人： Eric G. Webb ,  Jonathan D. Reid ,  Seyang Park ,  Johanes H. Sukamto

IPC分类号： C22F1/14

CPC分类号： C22F1/14 ,  C23C16/18 ,  C23C16/56 ,  H01L21/76862 ,  H01L21/76864 ,  H01L21/76873 ,  H01L21/76874

摘要： A ruthenium-containing thin film is formed. Typically, the ruthenium-containing thin film has a thickness in a range of about from 1 nm to 20 nm. The ruthenium-containing thin film is annealed in an oxygen-free atmosphere, for example, in N2 forming gas, at a temperature in a range of about from 100° C. to 500° C. for a total time duration of about from 10 seconds to 1000 seconds. Thereafter, copper or other metal is deposited by electroplating or electroless plating onto the annealed ruthenium-containing thin film. In some embodiments, the ruthenium-containing thin film is also treated by UV radiation.

摘要翻译： 形成含钌的薄膜。 通常，含钌薄膜的厚度在约1nm至20nm的范围内。 含钌的薄膜在无氧气氛中，例如在N 2 O 2形成气体中，在约100℃至500℃的温度范围内退火，以便 总时间约10秒至1000秒。 此后，通过电镀或化学镀将铜或其它金属沉积到退火的含钌薄膜上。 在一些实施方案中，含钌的薄膜也通过UV辐射处理。

公开(公告)号：US06664122B1

公开(公告)日：2003-12-16

申请号：US09996425

申请日：2001-11-27

申请人： Tatyana N. Andryuschenko ,  Jonathan D. Reid ,  Steven T. Mayer ,  Eric G. Webb

发明人： Tatyana N. Andryuschenko ,  Jonathan D. Reid ,  Steven T. Mayer ,  Eric G. Webb

IPC分类号： H01L2166

CPC分类号： H01L21/76843 ,  C23C18/1617 ,  C23C18/1669 ,  C23C18/1675 ,  C23C18/1676 ,  C23C18/168 ,  C23C18/1692 ,  C23C18/40 ,  H01L21/288 ,  H01L21/76864 ,  H01L21/76868 ,  H01L21/76873 ,  H01L2221/1089 ,  Y10S977/89

摘要： Disclosed is a procedure for deposition of a thin and relatively continuous electroless copper film on the substrate of sub-micron integrated circuit features. The electroless copper film is deposited onto a previously deposited PVD copper film, which may be discontinuous. The continuous film formed by electroless deposition allows for sufficient filling of the sub-micron integrated circuit features by electrodeposition. The electroless bath employed to form the continuous electroless copper film may be composed of a reducing agent, a complexing agent, a source of copper ions, a pH adjuster, and optionally one or more surfactants and/or stabilizers. In one example, the reducing agent contains an aldehyde moiety.

摘要翻译： 公开了在亚微米集成电路特征的衬底上沉积薄而相对连续的无电铜膜的步骤。 将化学镀铜膜沉积在预先沉积的PVD铜膜上，其可以是不连续的。 通过无电沉积形成的连续膜允许通过电沉积充分填充亚微米集成电路特征。 用于形成连续化学镀铜膜的无电镀浴可以由还原剂，络合剂，铜离子源，pH调节剂和任选的一种或多种表面活性剂和/或稳定剂组成。 在一个实例中，还原剂含有醛部分。

公开(公告)号：US08415261B1

公开(公告)日：2013-04-09

申请号：US13270809

申请日：2011-10-11

申请人： Jonathan D. Reid ,  Eric G. Webb ,  Edmund B. Minshall ,  Avishai Kepten ,  R. Marshall Stowell ,  Steven T. Mayer

发明人： Jonathan D. Reid ,  Eric G. Webb ,  Edmund B. Minshall ,  Avishai Kepten ,  R. Marshall Stowell ,  Steven T. Mayer

IPC分类号： H01L21/00 ,  B01J19/12

CPC分类号： H01L21/7684 ,  C23C18/1607 ,  C23C18/1882 ,  C25D5/02 ,  C25D7/123 ,  H01L21/02074 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76883 ,  Y10S414/135

摘要： Methods of forming a capping layer on conductive lines in a semiconductor device may be characterized by the following operations: (a) providing a semiconductor substrate comprising a dielectric layer having (i) exposed conductive lines (e.g., copper lines) disposed therein, and (ii) an exposed barrier layer disposed thereon; and (b) depositing a capping layer material on at least the exposed conductive lines of the semiconductor substrate. In certain embodiments, the method may also involve removing at least a portion of a conductive layer (e.g., overburden) disposed over the barrier layer and conductive lines to expose the barrier layer.

公开(公告)号：US07605082B1

公开(公告)日：2009-10-20

申请号：US11251353

申请日：2005-10-13

申请人： Jonathan D. Reid ,  Eric G. Webb ,  Edmund B. Minshall ,  Avishai Kepten ,  R. Marshall Stowell ,  Steven T. Mayer

发明人： Jonathan D. Reid ,  Eric G. Webb ,  Edmund B. Minshall ,  Avishai Kepten ,  R. Marshall Stowell ,  Steven T. Mayer

IPC分类号： H01L21/44

CPC分类号： H01L21/7684 ,  C23C18/1607 ,  C23C18/1882 ,  C25D5/02 ,  C25D7/123 ,  H01L21/02074 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76883 ,  Y10S414/135

摘要： Methods of forming a capping layer on conductive lines in a semiconductor device may be characterized by the following operations: (a) providing a semiconductor substrate comprising a dielectric layer having (i) exposed conductive lines (e.g., copper lines) disposed therein, and (ii) an exposed barrier layer disposed thereon; and (b) depositing a capping layer material on at least the exposed conductive lines of the semiconductor substrate. In certain embodiments, the method may also involve removing at least a portion of a conductive layer (e.g., overburden) disposed over the barrier layer and conductive lines to expose the barrier layer.

摘要翻译： 在半导体器件中的导电线上形成覆盖层的方法的特征在于以下操作：（a）提供包括介电层的半导体衬底，所述电介质层具有（i）设置在其中的暴露的导电线（例如铜线）和（ ii）设置在其上的暴露的阻挡层; 和（b）在所述半导体衬底的至少暴露的导电线上沉积覆盖层材料。 在某些实施例中，该方法还可以包括移除设置在阻挡层和导电线上的导电层（例如，覆盖层）的至少一部分以暴露阻挡层。

公开(公告)号：US07341946B2

公开(公告)日：2008-03-11

申请号：US10705579

申请日：2003-11-10

申请人： Sridhar K. Kailasam ,  John Drewery ,  Jonathan D. Reid ,  Eric G. Webb ,  Johanes H. Sukamto

发明人： Sridhar K. Kailasam ,  John Drewery ,  Jonathan D. Reid ,  Eric G. Webb ,  Johanes H. Sukamto

IPC分类号： H01L21/44

CPC分类号： H01L21/76843 ,  C25D7/12 ,  H01L21/2885 ,  H01L21/76856 ,  H01L21/76873 ,  H01L21/76877

摘要： Methods are provided for electrochemically depositing copper on a work piece. One method includes the step of depositing overlying the work piece a barrier layer having a surface and subjecting the barrier layer surface to a surface treatment adapted to facilitate deposition of copper on the barrier layer. Copper then is electrochemically deposited overlying the barrier layer.

公开(公告)号：US08043958B1

公开(公告)日：2011-10-25

申请号：US12875857

申请日：2010-09-03

申请人： Jonathan D. Reid ,  Eric G. Webb ,  Edmund B. Minshall ,  Avishai Kepten ,  R. Marshall Stowell ,  Steven T. Mayer

发明人： Jonathan D. Reid ,  Eric G. Webb ,  Edmund B. Minshall ,  Avishai Kepten ,  R. Marshall Stowell ,  Steven T. Mayer

IPC分类号： H01L21/302 ,  H01L21/461 ,  B24B7/00

CPC分类号： H01L21/7684 ,  C23C18/1607 ,  C23C18/1882 ,  C25D5/02 ,  C25D7/123 ,  H01L21/02074 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76883 ,  Y10S414/135

摘要： Methods of forming a capping layer on conductive lines in a semiconductor device may be characterized by the following operations: (a) providing a semiconductor substrate comprising a dielectric layer having (i) exposed conductive lines (e.g., copper lines) disposed therein, and (ii) an exposed barrier layer disposed thereon; and (b) depositing a capping layer material on at least the exposed conductive lines of the semiconductor substrate. In certain embodiments, the method may also involve removing at least a portion of a conductive layer (e.g., overburden) disposed over the barrier layer and conductive lines to expose the barrier layer.

摘要翻译： 在半导体器件中的导电线上形成覆盖层的方法的特征在于以下操作：（a）提供包括介电层的半导体衬底，所述电介质层具有（i）设置在其中的暴露的导电线（例如铜线）和（ ii）设置在其上的暴露的阻挡层; 和（b）在所述半导体衬底的至少暴露的导电线上沉积覆盖层材料。 在某些实施例中，该方法还可以包括移除设置在阻挡层和导电线上的导电层（例如，覆盖层）的至少一部分以暴露阻挡层。