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    SEMICONDUCTOR DEVICE COMPRISING NMOS AND PMOS TRANSISTORS WITH EMBEDDED SI/GE MATERIAL FOR CREATING TENSILE AND COMPRESSIVE STRAIN
    4.
    发明申请
    SEMICONDUCTOR DEVICE COMPRISING NMOS AND PMOS TRANSISTORS WITH EMBEDDED SI/GE MATERIAL FOR CREATING TENSILE AND COMPRESSIVE STRAIN 有权
    包含用于创建拉伸和压缩应变的嵌入式SI / GE材料的NMOS和PMOS晶体管的半导体器件

    公开(公告)号：US20100187635A1

    公开(公告)日：2010-07-29

    申请号：US12754819

    申请日：2010-04-06

    申请人： SVEN BEYER ,  Manfred Horstmann ,  Patrick Press ,  Wolfgang Buchholtz

    发明人： SVEN BEYER ,  Manfred Horstmann ,  Patrick Press ,  Wolfgang Buchholtz

    IPC分类号： H01L27/092 ,  H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L29/165 ,  H01L29/66621 ,  H01L29/66651 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/7849

    摘要： By forming a substantially continuous and uniform semiconductor alloy in one active region while patterning the semiconductor alloy in a second active region so as to provide a base semiconductor material in a central portion thereof, different types of strain may be induced, while, after providing a corresponding cover layer of the base semiconductor material, well-established process techniques for forming the gate dielectric may be used. In some illustrative embodiments, a substantially self-aligned process is provided in which the gate electrode may be formed on the basis of layer, which has also been used for defining the central portion of the base semiconductor material of one of the active regions. Hence, by using a single semiconductor alloy, the performance of transistors of different conductivity types may be individually enhanced.

    摘要翻译： 通过在一个有源区中形成基本上连续且均匀的半导体合金，同时在第二有源区中图案化半导体合金，以便在其中心部分提供基极半导体材料，可以诱发不同类型的应变， 可以使用基底半导体材料的相应的覆盖层，用于形成栅极电介质的完善的工艺技术。 在一些示例性实施例中，提供了基本上自对准的工艺，其中栅电极可以基于层形成，其也已经用于限定一个有源区的基极半导体材料的中心部分。 因此，通过使用单个半导体合金，可以单独提高不同导电类型的晶体管的性能。

    Field effect transistors and methods for fabricating the same
    5.
    发明授权
    Field effect transistors and methods for fabricating the same 有权
    场效应晶体管及其制造方法

    公开(公告)号：US07605045B2

    公开(公告)日：2009-10-20

    申请号：US11457300

    申请日：2006-07-13

    申请人： Igor Peidous ,  Patrick Press ,  Rolf Stephan

    发明人： Igor Peidous ,  Patrick Press ,  Rolf Stephan

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7843 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/7833

    摘要： Field effect transistors and methods for fabricating field effect transistors are provided. A method, in accordance with an exemplary embodiment of the invention, comprises forming a polycrystalline silicon gate electrode overlying a silicon substrate. The gate electrode has two parallel sidewalls. Two sidewall spacers are fabricated overlying the silicon substrate. Each of the two sidewall spacers has a sidewall that is adjacent to one of the two parallel sidewalls of the gate electrode. A portion of the gate electrode between the two sidewall spacers is removed.

    摘要翻译： 提供场效应晶体管和制造场效应晶体管的方法。 根据本发明的示例性实施例的方法包括形成覆盖硅衬底的多晶硅栅电极。 栅电极具有两个平行的侧壁。 在硅衬底上制造两个侧壁间隔物。 两个侧壁间隔物中的每一个具有与栅电极的两个平行侧壁中的一个相邻的侧壁。 去除两个侧壁间隔物之间​​的栅电极的一部分。

    METHODS FOR FABRICATING LOW CONTACT RESISTANCE CMOS CIRCUITS
    6.
    发明申请
    METHODS FOR FABRICATING LOW CONTACT RESISTANCE CMOS CIRCUITS 有权
    制造低接触电阻CMOS电路的方法

    公开(公告)号：US20080182370A1

    公开(公告)日：2008-07-31

    申请号：US11669401

    申请日：2007-01-31

    申请人： Igor Peidous ,  Patrick Press ,  Paul R. Besser

    发明人： Igor Peidous ,  Patrick Press ,  Paul R. Besser

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/324 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/665

    摘要： Methods for fabricating low contact resistance CMOS integrated circuits are provided. In accordance with an embodiment, a method for fabricating a CMOS integrated circuit including an NMOS transistor and a PMOS transistor disposed in and on a silicon-comprising substrate includes depositing a first silicide-forming metal on the NMOS and PMOS transistors. The first silicide-forming metal forms a silicide at a first temperature. At least a portion of the first silicide-forming metal is removed from the NMOS or PMOS transistor and a second silicide-forming metal is deposited. The second silicide-forming metal forms a silicide at a second temperature that is different from the first temperature. The first silicide-forming metal and the second silicide-forming metal are heated at a temperature that is no less than the higher of the first temperature and the second temperature.

    摘要翻译： 提供了制造低接触电阻CMOS集成电路的方法。 根据实施例，一种制造包括设置在含硅衬底中的NMOS晶体管和PMOS晶体管的CMOS集成电路的方法包括在NMOS和PMOS晶体管上沉积第一硅化物形成金属。 第一硅化物形成金属在第一温度下形成硅化物。 第一硅化物形成金属的至少一部分从NMOS或PMOS晶体管去除，并且沉积第二硅化物形成金属。 第二硅化物形成金属在不同于第一温度的第二温度下形成硅化物。 第一硅化物形成金属和第二硅化物形成金属在不低于第一温度和第二温度的较高温度的温度下加热。

    Drive current adjustment for transistors by local gate engineering
    8.
    发明授权
    Drive current adjustment for transistors by local gate engineering 有权
    通过局部门工程驱动晶体管的电流调节

    公开(公告)号：US08188871B2

    公开(公告)日：2012-05-29

    申请号：US12472969

    申请日：2009-05-27

    申请人： Manfred Horstmann ,  Patrick Press ,  Karsten Wieczorek ,  Kerstin Ruttloff

    发明人： Manfred Horstmann ,  Patrick Press ,  Karsten Wieczorek ,  Kerstin Ruttloff

    IPC分类号： G08B17/00

    CPC分类号： H01L21/823462 ,  H01L21/28035 ,  H01L21/823456 ,  H01L27/11 ,  H01L29/4238 ,  H01L29/513

    摘要： In a memory cell, the drive current capabilities of the transistors may be adjusted by locally providing an increased gate dielectric thickness and/or gate length of one or more of the transistors of the memory cell. That is, the gate length and/or the gate dielectric thickness may vary along the transistor width direction, thereby providing an efficient mechanism for adjusting the effective drive current capability while at the same time allowing the usage of a simplified geometry of the active region, which may result in enhanced production yield due to enhanced process uniformity. In particular, the probability of creating short circuits caused by nickel silicide portions may be reduced.

    摘要翻译： 在存储器单元中，晶体管的驱动电流能力可以通过局部地提供存储单元的一个或多个晶体管的增加的栅介质厚度和/或栅极长度来调节。 也就是说，栅极长度和/或栅极电介质厚度可以沿晶体管宽度方向变化，从而提供用于调节有效驱动电流能力的有效机构，同时允许使用有源区域的简化几何形状， 这可能由于增加的工艺均匀性而导致产量提高。 特别地，可能减少由硅化镍部分引起的产生短路的可能性。

    Semiconductor device comprising NMOS and PMOS transistors with embedded Si/Ge material for creating tensile and compressive strain
    9.
    发明授权
    Semiconductor device comprising NMOS and PMOS transistors with embedded Si/Ge material for creating tensile and compressive strain 有权
    半导体器件包括具有嵌入的Si / Ge材料的NMOS和PMOS晶体管，用于产生拉伸和压缩应变

    公开(公告)号：US07893503B2

    公开(公告)日：2011-02-22

    申请号：US12754819

    申请日：2010-04-06

    申请人： Sven Beyer ,  Manfred Horstmann ,  Patrick Press ,  Wolfgang Buchholtz

    发明人： Sven Beyer ,  Manfred Horstmann ,  Patrick Press ,  Wolfgang Buchholtz

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L21/823807 ,  H01L29/165 ,  H01L29/66621 ,  H01L29/66651 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/7849

    摘要： By forming a substantially continuous and uniform semiconductor alloy in one active region while patterning the semiconductor alloy in a second active region so as to provide a base semiconductor material in a central portion thereof, different types of strain may be induced, while, after providing a corresponding cover layer of the base semiconductor material, well-established process techniques for forming the gate dielectric may be used. In some illustrative embodiments, a substantially self-aligned process is provided in which the gate electrode may be formed on the basis of layer, which has also been used for defining the central portion of the base semiconductor material of one of the active regions. Hence, by using a single semiconductor alloy, the performance of transistors of different conductivity types may be individually enhanced.

    摘要翻译： 通过在一个有源区中形成基本上连续且均匀的半导体合金，同时在第二有源区中图案化半导体合金，以便在其中心部分提供基极半导体材料，可以诱发不同类型的应变， 可以使用基底半导体材料的相应的覆盖层，用于形成栅极电介质的完善的工艺技术。 在一些示例性实施例中，提供了基本上自对准的工艺，其中栅电极可以基于层形成，其也已经用于限定一个有源区的基极半导体材料的中心部分。 因此，通过使用单个半导体合金，可以单独提高不同导电类型的晶体管的性能。