利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

37 条记录 (耗时 0.022 秒)

    Printed circuit embedded capacitors
    2.
    发明授权
    Printed circuit embedded capacitors 失效
    印刷电路嵌入式电容器

    公开(公告)号：US07056800B2

    公开(公告)日：2006-06-06

    申请号：US10736327

    申请日：2003-12-15

    申请人： Robert T. Croswell ,  Gregory J. Dunn ,  Robert B. Lempkowski ,  Aroon V. Tungare ,  Jovica Savic

    发明人： Robert T. Croswell ,  Gregory J. Dunn ,  Robert B. Lempkowski ,  Aroon V. Tungare ,  Jovica Savic

    IPC分类号： H01L21/20 ,  H01G4/00

    CPC分类号： H05K1/162 ,  H05K3/0029 ,  H05K3/025 ,  H05K3/384 ,  H05K3/429 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09718

    摘要： One of a plurality of capacitors embedded in a printed circuit structure includes a first electrode (415) overlaying a first substrate layer (505) of the printed circuit structure, a crystallized dielectric oxide core (405) overlaying the first electrode, a second electrode (615) overlying the crystallized dielectric oxide core, and a high temperature anti-oxidant layer (220) disposed between and contacting the crystallized dielectric oxide core and at least one of the first and second electrodes. The crystallized dielectric oxide core has a thickness that is less than 1 micron and has a capacitance density greater than 1000 pF/mm2. The material and thickness are the same for each of the plurality of capacitors. The crystallized dielectric oxide core may be isolated from crystallized dielectric oxide cores of all other capacitors of the plurality of capacitors.

    摘要翻译： 嵌入印刷电路结构中的多个电容器之一包括覆盖印刷电路结构的第一衬底层（505）的第一电极（415），覆盖第一电极的结晶化电介质氧化物芯（405），第二电极 615），以及设置在结晶的电介质氧化物芯和第一和第二电极中的至少一个之间并与其接触的高温抗氧化剂层（220）。 结晶的电介质氧化物芯的厚度小于1微米，电容密度大于1000pF / mm 2。 多个电容器的材料和厚度相同。 结晶的电介质氧化物芯可以与多个电容器的所有其它电容器的结晶的电介质氧化物芯隔离。

    Capacitance laminate and printed circuit board apparatus and method
    3.
    发明授权
    Capacitance laminate and printed circuit board apparatus and method 失效
    电容层压板和印刷电路板装置及方法

    公开(公告)号：US07361847B2

    公开(公告)日：2008-04-22

    申请号：US11323515

    申请日：2005-12-30

    申请人： Gregory J. Dunn ,  Jaroslaw A. Magera ,  Jovica Savic

    发明人： Gregory J. Dunn ,  Jaroslaw A. Magera ,  Jovica Savic

    IPC分类号： H05K1/16

    CPC分类号： H05K1/162 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09718

    摘要： A method is for fabricating an embedded capacitance printed circuit board assembly (400, 1100). The embedded capacitance printed circuit board assembly includes two embedded capacitance structures (110). Each capacitance structure (110) includes a crystallized dielectric oxide layer (115) sandwiched between an outer electrode layer (120) and an inner electrode layer (125) in which the two inner electrode layers are electrically connected together. A rivet via (1315) and a stacked via (1110) formed from a button via (910) and a stacked blind via (1111) may be used to electrically connect the two inner electrode layers together. A spindle via (525) may be formed through the inner and outer layers. The multi-layer printed circuit board may be formed from a capacitive laminate (100) that includes two capacitance structures.

    摘要翻译： 一种用于制造嵌入式电容印刷电路板组件（400,1100）的方法。 嵌入式电容印刷电路板组件包括两个嵌入式电容结构（110）。 每个电容结构（110）包括夹在两个内部电极层电连接在一起的外部电极层（120）和内部电极层（125）之间的结晶化电介质氧化物层（115）。 可以使用铆钉通孔（1315）和由按钮通孔（910）和堆叠的通孔（1111）形成的堆叠通孔（1110）将两个内部电极层电连接在一起。 主轴通孔（525）可以通过内层和外层形成。 多层印刷电路板可以由包括两个电容结构的电容层压板（100）形成。

    Meso-microelectromechanical system having a glass beam and method for its fabrication
    7.
    发明授权
    Meso-microelectromechanical system having a glass beam and method for its fabrication 有权
    具有玻璃束的中微机电系统及其制造方法

    公开(公告)号：US07217369B2

    公开(公告)日：2007-05-15

    申请号：US11380983

    申请日：2006-05-01

    申请人： Jovica Savic ,  Manes Eliacin ,  Junhua Liu ,  Aroon V. Tungare

    发明人： Jovica Savic ,  Manes Eliacin ,  Junhua Liu ,  Aroon V. Tungare

    IPC分类号： C23F1/00 ,  H01L21/00

    CPC分类号： H02N1/006 ,  G02B26/0841

    摘要： A meso-electromechanical system (900, 1100) includes a substrate (215), a standoff (405, 1160) disposed on a surface of the substrate, a first electrostatic pattern (205, 1105, 1110, 1115, 1120) disposed on the surface of the substrate, and a glass beam (810). The glass beam (810) has a fixed region (820) attached to the standoff and has a second electrostatic pattern (815, 1205, 1210, 1215, 1220) on a cantilevered location of the glass beam. The second electrostatic pattern is substantially co-extensive with and parallel to the first electrostatic pattern. The second electrostatic pattern has a relaxed separation (925) from the first electrostatic pattern when the first and second electrostatic patterns are in a non-energized state. In some embodiments, a mirror is formed by the electrostatic materials that form the second electrostatic pattern. The glass beam may be patterned using sandblasting (140).

    摘要翻译： 中间机电系统（900,1100）包括衬底（215），设置在衬底的表面上的支座（405,1160），设置在衬底上的第一静电图案（205,1105,1110,1115,1120） 基板的表面和玻璃光束（810）。 玻璃束（810）具有附接到支座的固定区域（820），并且在玻璃束的悬臂位置上具有第二静电图案（815,1205,1212,1215,1220）。 第二静电图案与第一静电图案基本上共同并且平行。 当第一静电图案和第二静电图案处于非通电状态时，第二静电图案具有与第一静电图案的松弛分离（925）。 在一些实施例中，由形成第二静电图案的静电材料形成反射镜。 可以使用喷砂将玻璃束图案化（140）。

    Method for manufacturing an integral thin-film metal resistor
    9.
    发明授权
    Method for manufacturing an integral thin-film metal resistor 失效
    制造整体薄膜金属电阻的方法

    公开(公告)号：US06232042B1

    公开(公告)日：2001-05-15

    申请号：US09111189

    申请日：1998-07-07

    申请人： Gregory J. Dunn ,  Jovica Savic ,  Allyson Beuhler

    发明人： Gregory J. Dunn ,  Jovica Savic ,  Allyson Beuhler

    IPC分类号： G03F700

    CPC分类号： H05K1/167 ,  G03F7/00 ,  H01C17/07 ,  H05K3/0023 ,  H05K3/025 ,  H05K3/048 ,  H05K3/386 ,  H05K2201/0317 ,  H05K2201/09881 ,  H05K2203/0152 ,  H05K2203/1461

    摘要： A method for manufacturing a microelectronic assembly to have a resistor, and particularly a metal resistive film, with desirable processing and dimensional characteristics. The method generally entails applying a photosensitive dielectric to a substrate to form a dielectric layer. The dielectric layer is photoimaged to polymerize a first portion of the dielectric layer on a first region of the substrate, leaving the remainder of the dielectric layer unpolymerized. An electrically resistive film is then applied to the dielectric layer, and the dielectric layer is developed to remove concurrently the unpolymerized portion thereof and the portion of the resistive film overlying the unpolymerized portion, so that a portion of the resistive film remains over the second portion to form the resistor. An alternative process order is to apply the resistive film prior to exposing the dielectric layer to radiation, and then exposing the dielectric layer through the resistive film. The resistive film is preferably a multilayer film that includes an electrically resistive layer, such as NiP, NiCr or another nickel-containing alloy, and a sacrificial backing such as a layer of copper.

    摘要翻译： 一种用于制造具有所需加工和尺寸特性的电阻器，特别是金属电阻膜的微电子组件的方法。 该方法通常需要将光敏电介质施加到衬底以形成电介质层。 介电层被光刻以在基板的第一区域上聚合电介质层的第一部分，留下介电层的其余部分未聚合。 然后将电阻膜施加到电介质层，并且电介质层被显影以同时除去其未聚合部分和覆盖未聚合部分的电阻膜的部分，使得电阻膜的一部分保留在第二部分上 以形成电阻器。 替代的处理顺序是在将电介质层暴露于辐射之前施加电阻膜，然后将电介质层暴露于电阻膜。 电阻膜优选为包含电阻层的多层膜，例如NiP，NiCr或其它含镍合金，以及牺牲衬底，例如铜层。