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    Printed circuit embedded capacitors
    3.
    发明授权
    Printed circuit embedded capacitors 失效
    印刷电路嵌入式电容器

    公开(公告)号：US07056800B2

    公开(公告)日：2006-06-06

    申请号：US10736327

    申请日：2003-12-15

    申请人： Robert T. Croswell ,  Gregory J. Dunn ,  Robert B. Lempkowski ,  Aroon V. Tungare ,  Jovica Savic

    发明人： Robert T. Croswell ,  Gregory J. Dunn ,  Robert B. Lempkowski ,  Aroon V. Tungare ,  Jovica Savic

    IPC分类号： H01L21/20 ,  H01G4/00

    CPC分类号： H05K1/162 ,  H05K3/0029 ,  H05K3/025 ,  H05K3/384 ,  H05K3/429 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09718

    摘要： One of a plurality of capacitors embedded in a printed circuit structure includes a first electrode (415) overlaying a first substrate layer (505) of the printed circuit structure, a crystallized dielectric oxide core (405) overlaying the first electrode, a second electrode (615) overlying the crystallized dielectric oxide core, and a high temperature anti-oxidant layer (220) disposed between and contacting the crystallized dielectric oxide core and at least one of the first and second electrodes. The crystallized dielectric oxide core has a thickness that is less than 1 micron and has a capacitance density greater than 1000 pF/mm2. The material and thickness are the same for each of the plurality of capacitors. The crystallized dielectric oxide core may be isolated from crystallized dielectric oxide cores of all other capacitors of the plurality of capacitors.

    摘要翻译： 嵌入印刷电路结构中的多个电容器之一包括覆盖印刷电路结构的第一衬底层（505）的第一电极（415），覆盖第一电极的结晶化电介质氧化物芯（405），第二电极 615），以及设置在结晶的电介质氧化物芯和第一和第二电极中的至少一个之间并与其接触的高温抗氧化剂层（220）。 结晶的电介质氧化物芯的厚度小于1微米，电容密度大于1000pF / mm 2。 多个电容器的材料和厚度相同。 结晶的电介质氧化物芯可以与多个电容器的所有其它电容器的结晶的电介质氧化物芯隔离。

    Peelable circuit board foil
    4.
    发明授权
    Peelable circuit board foil 失效
    可剥离电路板箔

    公开(公告)号：US06872468B1

    公开(公告)日：2005-03-29

    申请号：US10682557

    申请日：2003-10-09

    申请人： Timothy B. Dean ,  Gregory J. Dunn ,  Remy J. Chelini ,  Claudia V. Gamboa

    发明人： Timothy B. Dean ,  Gregory J. Dunn ,  Remy J. Chelini ,  Claudia V. Gamboa

    IPC分类号： H05K1/16 ,  H05K3/02 ,  H05K3/38 ,  B21C37/02

    CPC分类号： H05K1/162 ,  H05K3/025 ,  H05K3/384 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0355 ,  Y10T428/12493 ,  Y10T428/1259 ,  Y10T428/12611 ,  Y10T428/12667 ,  Y10T428/12875 ,  Y10T428/12882 ,  Y10T428/24917

    摘要： In one embodiment, a peelable circuit board foil (200) has a metal support layer (205) and a conductive metal foil layer (210) bonded by an inorganic release material (215). The conductive metal foil layer has a an exposed surface (212) that is coated with a high temperature anti-oxidant barrier (220) and has a roughness less than 0.05 microns RMS. In a second embodiment, the peelable printed circuit foil (200) has a crystallized dielectric oxide layer (405) disposed on the exposed surface of the conductive metal foil layer and an electrode layer (415) disposed on the crystallized dielectric oxide layer, forming a dielectric peelable circuit board foil (400) that may be adhered to a layer of a flexible or rigid circuit board, after which the metal support layer can be peeled away, leaving a capacitive structure including the metal foil layer, the crystallized dielectric oxide layer, and the electrode layer.

    摘要翻译： 在一个实施例中，可剥离电路板箔（200）具有通过无机剥离材料（215）粘合的金属支撑层（205）和导电金属箔层（210）。 导电金属箔层具有涂覆有高温抗氧化剂屏障（220）并具有小于0.05微米RMS的粗糙度的暴露表面（212）。 在第二实施例中，可剥离印刷电路箔（200）具有设置在导电金属箔层的暴露表面上的结晶的电介质氧化物层（405）和设置在结晶的电介质氧化物层上的电极层（415），形成 可以粘附到柔性或刚性电路板的层的介电可剥离电路板箔（400），之后金属支撑层可以被剥离，留下包括金属箔层，结晶化电介质氧化物层， 和电极层。

    Method for manufacturing an integral thin-film metal resistor
    6.
    发明授权
    Method for manufacturing an integral thin-film metal resistor 失效
    制造整体薄膜金属电阻的方法

    公开(公告)号：US06232042B1

    公开(公告)日：2001-05-15

    申请号：US09111189

    申请日：1998-07-07

    申请人： Gregory J. Dunn ,  Jovica Savic ,  Allyson Beuhler

    发明人： Gregory J. Dunn ,  Jovica Savic ,  Allyson Beuhler

    IPC分类号： G03F700

    CPC分类号： H05K1/167 ,  G03F7/00 ,  H01C17/07 ,  H05K3/0023 ,  H05K3/025 ,  H05K3/048 ,  H05K3/386 ,  H05K2201/0317 ,  H05K2201/09881 ,  H05K2203/0152 ,  H05K2203/1461

    摘要： A method for manufacturing a microelectronic assembly to have a resistor, and particularly a metal resistive film, with desirable processing and dimensional characteristics. The method generally entails applying a photosensitive dielectric to a substrate to form a dielectric layer. The dielectric layer is photoimaged to polymerize a first portion of the dielectric layer on a first region of the substrate, leaving the remainder of the dielectric layer unpolymerized. An electrically resistive film is then applied to the dielectric layer, and the dielectric layer is developed to remove concurrently the unpolymerized portion thereof and the portion of the resistive film overlying the unpolymerized portion, so that a portion of the resistive film remains over the second portion to form the resistor. An alternative process order is to apply the resistive film prior to exposing the dielectric layer to radiation, and then exposing the dielectric layer through the resistive film. The resistive film is preferably a multilayer film that includes an electrically resistive layer, such as NiP, NiCr or another nickel-containing alloy, and a sacrificial backing such as a layer of copper.

    摘要翻译： 一种用于制造具有所需加工和尺寸特性的电阻器，特别是金属电阻膜的微电子组件的方法。 该方法通常需要将光敏电介质施加到衬底以形成电介质层。 介电层被光刻以在基板的第一区域上聚合电介质层的第一部分，留下介电层的其余部分未聚合。 然后将电阻膜施加到电介质层，并且电介质层被显影以同时除去其未聚合部分和覆盖未聚合部分的电阻膜的部分，使得电阻膜的一部分保留在第二部分上 以形成电阻器。 替代的处理顺序是在将电介质层暴露于辐射之前施加电阻膜，然后将电介质层暴露于电阻膜。 电阻膜优选为包含电阻层的多层膜，例如NiP，NiCr或其它含镍合金，以及牺牲衬底，例如铜层。

    Circuit board features with reduced parasitic capacitance and method therefor
    10.
    发明授权
    Circuit board features with reduced parasitic capacitance and method therefor 失效
    电路板具有降低的寄生电容及其方法

    公开(公告)号：US6103134A

    公开(公告)日：2000-08-15

    申请号：US224011

    申请日：1998-12-31

    申请人： Gregory J. Dunn ,  Larry Lach ,  Jovica Savic ,  Allyson Beuhler ,  Everett Simons

    发明人： Gregory J. Dunn ,  Larry Lach ,  Jovica Savic ,  Allyson Beuhler ,  Everett Simons

    IPC分类号： H01F17/00 ,  H01F41/04 ,  H01L21/768 ,  H01L23/522 ,  H05K1/16 ,  H05K3/00 ,  H05K3/06 ,  H05K3/46

    CPC分类号： H05K3/0082 ,  H01F41/041 ,  H01F41/046 ,  H05K1/165 ,  H05K3/0023 ,  H01F17/0013 ,  H05K2201/0187 ,  H05K2201/0355 ,  H05K2201/086 ,  H05K2201/09236 ,  H05K2203/0551 ,  H05K3/4652

    摘要： A method for fabricating circuit board conductors with desirable processing and reduced self and mutual capacitance. The method generally entails forming a metal layer on a positive-acting photodielectric layer formed on a substrate, and then etching the metal layer to form at least two conductor traces that cover two separate regions of the photodielectric layer while exposing a third region of the photodielectric layer between the two regions. The third region of the photodielectric layer is then irradiated and developed using the two traces as a photomask, so that the third region of the photodielectric layer is removed. The two remaining regions of the photodielectric layer masked by the traces remain on the substrate and are separated by an opening formed by the removal of the third dielectric region. As a result, the traces are not only separated by a void immediately therebetween formed when the metal layer was etched, but are also separated by the opening formed in the photodielectric layer by the removal of the third region of the photodielectric layer. Traces formed in accordance with the above may be formed as adjacent and parallel conductors or adjacent inductor windings of an integral inductor.

    摘要翻译： 一种用于制造具有所需加工和减小的自相互电容的电路板导体的方法。 该方法通常需要在形成在衬底上的正性作用的光致电介质层上形成金属层，然后蚀刻金属层以形成覆盖光致介电层的两个分离区域的至少两个导体迹线，同时暴露光致介电层的第三区域 两个地区之间。 然后使用两条迹线作为光掩模来照射和显影光致电介质层的第三区域，从而去除光致电介质层的第三区域。 由迹线掩蔽的光电介质层的两个剩余区域保留在基板上，并由通过去除第三介电区域形成的开口分开。 结果，痕迹不仅仅在金属层被蚀刻时形成的空隙之间分开，而且还通过去除光致电介质层的第三区域而被形成在光致电介质层中的开口分开。 根据上述形成的迹线可以形成为整体电感器的相邻和平行的导体或相邻的电感器绕组。