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公开(公告)号：US5786230A
公开(公告)日：1998-07-28
申请号：US431865
申请日：1995-05-01
IPC分类号： H01L23/15 , H01L21/60 , H01L23/14 , H01L23/31 , H01L23/36 , H01L23/367 , H01L23/538
CPC分类号： H01L24/95 , H01L23/147 , H01L23/3121 , H01L23/36 , H01L23/3672 , H01L24/37 , H01L24/40 , H01L24/81 , H01L24/84 , H01L2224/16 , H01L2224/37147 , H01L2224/40225 , H01L2224/81801 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/014 , H01L2924/1305 , H01L2924/13055 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15787
摘要： A method of fabricating a multi-chip package including an aluminum silicon substrate with an aluminum nitride layer thereon forming an electrically insulated surface and aluminum heat conductive areas positioned on the insulated surface. Conductors on the surface of the substrate defining mounting areas and external connections with each mounting area positioned adjacent an associated one of the heat conductive areas and a semiconductor chip mounted in each mounting area. Heat conductive elements connected to the rear surface of each chip and to the associated one of the plurality of heat conductive areas, and each chip encapsulated with reworkable encapsulant.
摘要翻译： 一种制造包括形成电绝缘表面的铝硅衬底的铝硅衬底和位于绝缘表面上的铝导热区域的多芯片封装的方法。 衬底表面上的导体限定了安装区域和外部连接，每个安装区域邻近相关联的一个导热区域以及安装在每个安装区域中的半导体芯片。 导热元件连接到每个芯片的后表面，并连接到多个导热区域中的相关联的一个，每个芯片封装有可再加工的密封剂。
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公开(公告)号：US5371043A
公开(公告)日：1994-12-06
申请号：US255533
申请日：1994-05-25
IPC分类号： H01L23/02 , H01L23/373 , H01L23/473 , H01L25/07 , H03B1/00 , H03B7/06 , H01L21/60
CPC分类号： H01L25/072 , H01L23/3731 , H01L2924/0002 , H01L2924/3011 , H03B2200/0034 , H03B2200/004 , H03B2201/0208 , H03B7/06 , Y10T29/4913
摘要： A method for forming a power circuit package (45) having a porous base structure (20) electrically isolated from a first porous die mount (21) and a second porous die mount (22) by a dielectric material (29). The porous base structure (20) is bonded to a second surface of the the dielectric material (29) whereas the first porous die mount (21 ) , and the second porous die mount (22 ) are bonded to a first surface of the dielectric material (29). Simultaneous with the bonding step, the porous base structure (20) , the first porous die mount (21) , and the second porous die mount (22) are impregnated with a conductive material. Semiconductor die (32, 33, 34, and 35) are bonded to the impregnated die mounts. The semiconductor die (32, 33, 34, and 35) are then encapsulated by a molding compound.
摘要翻译： 一种用于形成具有通过介电材料（29）与第一多孔管芯安装件（21）电隔离的多孔基底结构（20）和第二多孔管芯安装件（22）的电源电路封装（45）的方法。 所述多孔基底结构（20）与所述电介质材料（29）的第二表面接合，而所述第一多孔模座（21）和所述第二多孔模座（22）与所述电介质材料 （29）。 与接合步骤同时，多孔基底结构（20），第一多孔模座（21）和第二多孔模座（22）浸渍有导电材料。 半导体管芯（32,33,34和35）与浸渍的模具安装座结合。 然后，半导体管芯（32,33,34和35）被模塑料包封。
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公开(公告)号：US5616886A
公开(公告)日：1997-04-01
申请号：US464112
申请日：1995-06-05
IPC分类号： H01L23/12 , H01L23/057 , H01L23/498 , H01L25/04 , H01L25/18 , H01L23/02
CPC分类号： H01L24/82 , H01L23/057 , H01L23/49861 , H01L24/24 , H01L2224/24137 , H01L2224/24227 , H01L2924/01004 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/1305 , H01L2924/13055 , H01L2924/15787 , H01L2924/30107
摘要： A wirebondless module package and method of fabrication including a molded preform of porous SiC with a cavity having therein an AlN substrate defining a plurality of pockets. The preform being infiltrated with Al and the Al being deposited in each of the pockets. A semiconductor die mounted on the Al in one of the pockets. A dielectric layer covering the Al and defining openings therethrough positioned to expose the aluminum and a connection to the die. A conductive material positioned on the dielectric layer in contact with the die and the Al so as to define terminals and interconnections between the die and the terminals.
摘要翻译： 一种无引线模块封装和制造方法，包括多孔SiC的模制预制件，其中具有限定多个凹穴的AlN衬底的空腔。 预制件被Al渗透，并且Al沉积在每个口袋中。 安装在其中一个凹穴中的Al上的半导体管芯。 覆盖Al并且限定穿过其中的开口的介电层，以暴露铝和与管芯的连接。 位于电介质层上的与导体和Al接触的导电材料，以便限定晶片和端子之间的端子和互连。
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公开(公告)号：US5666269A
公开(公告)日：1997-09-09
申请号：US741576
申请日：1996-10-28
IPC分类号： H01L23/473 , H05K7/20
CPC分类号： H01L23/473 , F28F3/12 , H01L2924/0002 , Y10S428/901
摘要： A liquid cooled power dissipation apparatus (10) includes a metal matrix composite heat sink (11) with an insulation layer (17) integral to the apparatus (10). The insulation layer (17) is made integral to the apparatus (10) during infiltration of the metal matrix composite heat sink (11). Electronic components 23 are situated on top of the insulation layer (17).
摘要翻译： 液体冷却功率消耗装置（10）包括具有与装置（10）成一体的绝缘层（17）的金属基质复合散热器（11）。 在金属基体复合散热器（11）的渗透期间，绝缘层（17）与装置（10）成一体。 电子部件23位于绝缘层（17）的顶部。
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公开(公告)号：US5508559A
公开(公告)日：1996-04-16
申请号：US233100
申请日：1994-04-25
IPC分类号： H01L23/02 , H01L23/373 , H01L23/473 , H01L25/07 , H03B1/00 , H03B7/06 , H01L23/06
CPC分类号： H01L25/072 , H01L23/3731 , H01L2924/0002 , H01L2924/3011 , H03B2200/0034 , H03B2200/004 , H03B2201/0208 , H03B7/06 , Y10T29/4913
摘要： A method for forming a power circuit package (45) having a porous base structure (20) electrically isolated from a first porous die mount (21) and a second porous die mount (22) by a dielectric material (29). The porous base structure (20) is bonded to a second surface of the the dielectric material (29) whereas the first porous die mount (21), and the second porous die mount (22) are bonded to a first surface of the dielectric material (29). Simultaneous with the bonding step, the porous base structure (20), the first porous die mount (21), and the second porous die mount (22) are impregnated with a conductive material. Semiconductor die (32, 33, 34, and 35) are bonded to the impregnated die mounts. The semiconductor die (32, 33, 34, and 35) are then encapsulated by a molding compound.
摘要翻译： 一种用于形成具有通过介电材料（29）与第一多孔管芯安装件（21）电隔离的多孔基底结构（20）和第二多孔管芯安装件（22）的电源电路封装（45）的方法。 所述多孔基底结构（20）与所述电介质材料（29）的第二表面接合，而所述第一多孔模座（21）和所述第二多孔模座（22）与所述电介质材料 （29）。 与接合步骤同时，多孔基底结构（20），第一多孔模座（21）和第二多孔模座（22）浸渍有导电材料。 半导体管芯（32,33,34和35）与浸渍的模具安装座结合。 然后，半导体管芯（32,33,34和35）被模塑料包封。
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公开(公告)号：US09535830B2
公开(公告)日：2017-01-03
申请号：US14809263
申请日：2015-07-26
CPC分类号： G06F12/0246 , G06F3/0613 , G06F3/0655 , G06F3/0664 , G06F3/0679 , G06F3/068 , G06F12/121 , G06F2212/1044 , G06F2212/152 , G06F2212/2022 , G06F2212/7202 , G06F2212/7207 , G06F2212/7211
摘要： A device, memory, method and system directed to fast data storage on a block storage device. New data is written to an empty write block. A location of the new data is tracked. Meta data associated with the new data is written. A lookup table may be updated based in part on the meta data. The new data may be read based the lookup table configured to map a logical address to a physical address.
摘要翻译： 指向块存储设备上的快速数据存储的设备，存储器，方法和系统。 新数据写入空写入块。 跟踪新数据的位置。 写入与新数据相关联的元数据。 可以部分地基于元数据来更新查找表。 可以基于配置为将逻辑地址映射到物理地址的查找表来读取新数据。
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公开(公告)号：US20110140200A1
公开(公告)日：2011-06-16
申请号：US12978476
申请日：2010-12-24
IPC分类号： H01L27/06
CPC分类号： H01L29/7835 , H01L21/84 , H01L27/0629 , H01L27/1203 , H01L29/0619 , H01L29/1045 , H01L29/1087 , H01L29/66143 , H01L29/66659 , H01L29/872 , H01L2224/0401 , H01L2224/04042 , H01L2224/05572 , H01L2924/0002 , H01L2924/12032 , H01L2924/13091 , H01L2924/00 , H01L2224/05552
摘要： A semiconductor device includes a substrate having a first region and a second region. The first region is electrically isolated from the second region. The semiconductor device further includes a lateral field-effect transistor (FET) disposed within the first region. The lateral FET includes a first terminal and a second terminal. The semiconductor device further includes a diode disposed within the second region, the diode including a plurality of anode regions and a plurality of cathode regions. The semiconductor device further includes a first electrical connection between the first terminal of the lateral FET and the anode regions of the diode, and a second electrical connection between the second terminal of the lateral FET and the cathode regions of the diode. The first and second electrical connections are disposed over a surface of the substrate.
摘要翻译： 半导体器件包括具有第一区域和第二区域的衬底。 第一区域与第二区域电隔离。 半导体器件还包括设置在第一区域内的横向场效应晶体管（FET）。 横向FET包括第一端子和第二端子。 半导体器件还包括设置在第二区域内的二极管，二极管包括多个阳极区域和多个阴极区域。 半导体器件还包括横向FET的第一端子和二极管的阳极区域之间的第一电连接以及横向FET的第二端子和二极管的阴极区域之间的第二电连接。 第一和第二电连接设置在基板的表面上。
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8.发明申请Semiconductor Device and Method of Forming Lateral Power MOSFET with Integrated Schottky Diode on Monolithic Substrate 审中-公开半导体器件和在整体衬底上形成集成肖特基二极管的侧向功率MOSFET的方法公开(公告)号：US20090321784A1
公开(公告)日：2009-12-31
申请号：US12490112
申请日：2009-06-23
IPC分类号： H01L25/07 , H01L21/328
CPC分类号： H01L29/872 , H01L24/05 , H01L24/13 , H01L27/0629 , H01L27/0727 , H01L29/47 , H01L29/66128 , H01L29/66143 , H01L29/8611 , H01L2224/02166 , H01L2224/04042 , H01L2224/11 , H01L2224/48463 , H01L2924/01322 , H01L2924/12032 , H01L2924/12036 , H01L2924/12041 , H01L2924/1306 , H01L2924/13091 , H01L2924/30107 , H01L2924/00
摘要： A monolithic semiconductor device has an insulating layer formed over a first substrate. A second substrate is disposed over the first insulating layer. A power MOSFET with body diode is formed over the second substrate. A Schottky diode is formed over the second substrate in proximity to the MOSFET. An insulation trench is formed within the second substrate between the MOSFET and Schottky diode. The isolation trench surrounds the MOSFET and first Schottky diode. A first electrical connection is formed between a source of the MOSFET and an anode of the Schottky diode. A second electrical connection is formed between a drain of the MOSFET and a cathode of the Schottky diode. The Schottky diode reduces charge build-up within the body diode and reverse recovery time of the first power MOSFET. The power MOSFET and integrated Schottky can be used in power conversion or audio amplifier circuit.
摘要翻译： 单片半导体器件具有形成在第一衬底上的绝缘层。 第二基板设置在第一绝缘层上。 在第二基板上形成具有体二极管的功率MOSFET。 肖特基二极管形成在靠近MOSFET的第二衬底上。 在MOSFET和肖特基二极管之间的第二衬底内形成绝缘沟槽。 隔离沟围绕MOSFET和第一肖特基二极管。 在MOSFET的源极和肖特基二极管的阳极之间形成第一电连接。 在MOSFET的漏极和肖特基二极管的阴极之间形成第二电连接。 肖特基二极管可减少体二极管内的电荷积聚和第一功率MOSFET的反向恢复时间。 功率MOSFET和集成肖特基可用于电源转换或音频放大器电路。
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公开(公告)号：US5504351A
公开(公告)日：1996-04-02
申请号：US348413
申请日：1994-12-02
申请人： Samuel J. Anderson
发明人： Samuel J. Anderson
IPC分类号： H01L29/739 , H01L29/74 , H01L31/111
CPC分类号： H01L29/7395
摘要： A method of forming an insulated gate semiconductor device (10). A field effect transistor and a bipolar transistor are formed in a portion of a monocrystalline semiconductor substrate (11) that is bounded by a first major surface (12). A control electrode (19) is isolated from the first major surface by a dielectric layer (18). A first current conducting electrode (23) contacts a portion of the first major surface (12). A second current conducting electrode (24) contacts another portion of the monocrystalline semiconductor substrate (11) and is capable of injecting minority carriers into the monocrystalline semiconductor substrate (11). In one embodiment, the second current conducting electrode contacts a second major surface (13) of the monocrystalline semiconductor substrate (11).
摘要翻译： 一种形成绝缘栅半导体器件（10）的方法。 在由第一主表面（12）限定的单晶半导体衬底（11）的一部分中形成场效应晶体管和双极晶体管。 控制电极（19）通过电介质层（18）与第一主表面隔离。 第一电流导电电极（23）接触第一主表面（12）的一部分。 第二电流导电电极（24）接触单晶半导体衬底（11）的另一部分，并且能够将少数载流子注入到单晶半导体衬底（11）中。 在一个实施例中，第二电流传导电极接触单晶半导体衬底（11）的第二主表面（13）。
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公开(公告)号：US11455099B1
公开(公告)日：2022-09-27
申请号：US17079031
申请日：2020-10-23
IPC分类号： G06F3/06
摘要： A device, memory, method and system directed to fast data storage on a block storage device that reduces operational wear on the device. New data is written to an empty write block with a number of write blocks being reused. A location of the new data is tracked. Metadata associated with the new data is written. A lookup table may be updated based in part on the metadata. The new data may be read based the lookup table configured to map a logical address to a physical address.
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