公开(公告)号：US20120205740A9

公开(公告)日：2012-08-16

申请号：US12978476

申请日：2010-12-24

申请人： Samuel J. Anderson ,  David N. Okada ,  Gary Dashney ,  David A. Shumate

发明人： Samuel J. Anderson ,  David N. Okada ,  Gary Dashney ,  David A. Shumate

IPC分类号： H01L27/06

CPC分类号： H01L29/7835 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/0619 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/66143 ,  H01L29/66659 ,  H01L29/872 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05572 ,  H01L2924/0002 ,  H01L2924/12032 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/05552

摘要： A semiconductor device includes a substrate having a first region and a second region. The first region is electrically isolated from the second region. The semiconductor device further includes a lateral field-effect transistor (FET) disposed within the first region. The lateral FET includes a first terminal and a second terminal. The semiconductor device further includes a diode disposed within the second region, the diode including a plurality of anode regions and a plurality of cathode regions. The semiconductor device further includes a first electrical connection between the first terminal of the lateral FET and the anode regions of the diode, and a second electrical connection between the second terminal of the lateral FET and the cathode regions of the diode. The first and second electrical connections are disposed over a surface of the substrate.

摘要翻译： 半导体器件包括具有第一区域和第二区域的衬底。 第一区域与第二区域电隔离。 半导体器件还包括设置在第一区域内的横向场效应晶体管（FET）。 横向FET包括第一端子和第二端子。 半导体器件还包括设置在第二区域内的二极管，二极管包括多个阳极区域和多个阴极区域。 半导体器件还包括横向FET的第一端子和二极管的阳极区域之间的第一电连接以及横向FET的第二端子和二极管的阴极区域之间的第二电连接。 第一和第二电连接设置在基板的表面上。

公开(公告)号：US20110140200A1

公开(公告)日：2011-06-16

申请号：US12978476

申请日：2010-12-24

申请人： Samuel J. Anderson ,  David N. Okada ,  Gary Dashney ,  David A. Shumate

发明人： Samuel J. Anderson ,  David N. Okada ,  Gary Dashney ,  David A. Shumate

IPC分类号： H01L27/06

CPC分类号： H01L29/7835 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/0619 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/66143 ,  H01L29/66659 ,  H01L29/872 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05572 ,  H01L2924/0002 ,  H01L2924/12032 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/05552

摘要： A semiconductor device includes a substrate having a first region and a second region. The first region is electrically isolated from the second region. The semiconductor device further includes a lateral field-effect transistor (FET) disposed within the first region. The lateral FET includes a first terminal and a second terminal. The semiconductor device further includes a diode disposed within the second region, the diode including a plurality of anode regions and a plurality of cathode regions. The semiconductor device further includes a first electrical connection between the first terminal of the lateral FET and the anode regions of the diode, and a second electrical connection between the second terminal of the lateral FET and the cathode regions of the diode. The first and second electrical connections are disposed over a surface of the substrate.

摘要翻译： 半导体器件包括具有第一区域和第二区域的衬底。 第一区域与第二区域电隔离。 半导体器件还包括设置在第一区域内的横向场效应晶体管（FET）。 横向FET包括第一端子和第二端子。 半导体器件还包括设置在第二区域内的二极管，二极管包括多个阳极区域和多个阴极区域。 半导体器件还包括横向FET的第一端子和二极管的阳极区域之间的第一电连接以及横向FET的第二端子和二极管的阴极区域之间的第二电连接。 第一和第二电连接设置在基板的表面上。

公开(公告)号：US20090321784A1

公开(公告)日：2009-12-31

申请号：US12490112

申请日：2009-06-23

申请人： Samuel J. Anderson ,  David N. Okada ,  David A. Shumate ,  Gary Dashney

发明人： Samuel J. Anderson ,  David N. Okada ,  David A. Shumate ,  Gary Dashney

IPC分类号： H01L25/07 ,  H01L21/328

CPC分类号： H01L29/872 ,  H01L24/05 ,  H01L24/13 ,  H01L27/0629 ,  H01L27/0727 ,  H01L29/47 ,  H01L29/66128 ,  H01L29/66143 ,  H01L29/8611 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/11 ,  H01L2224/48463 ,  H01L2924/01322 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/30107 ,  H01L2924/00

摘要： A monolithic semiconductor device has an insulating layer formed over a first substrate. A second substrate is disposed over the first insulating layer. A power MOSFET with body diode is formed over the second substrate. A Schottky diode is formed over the second substrate in proximity to the MOSFET. An insulation trench is formed within the second substrate between the MOSFET and Schottky diode. The isolation trench surrounds the MOSFET and first Schottky diode. A first electrical connection is formed between a source of the MOSFET and an anode of the Schottky diode. A second electrical connection is formed between a drain of the MOSFET and a cathode of the Schottky diode. The Schottky diode reduces charge build-up within the body diode and reverse recovery time of the first power MOSFET. The power MOSFET and integrated Schottky can be used in power conversion or audio amplifier circuit.

摘要翻译： 单片半导体器件具有形成在第一衬底上的绝缘层。 第二基板设置在第一绝缘层上。 在第二基板上形成具有体二极管的功率MOSFET。 肖特基二极管形成在靠近MOSFET的第二衬底上。 在MOSFET和肖特基二极管之间的第二衬底内形成绝缘沟槽。 隔离沟围绕MOSFET和第一肖特基二极管。 在MOSFET的源极和肖特基二极管的阳极之间形成第一电连接。 在MOSFET的漏极和肖特基二极管的阴极之间形成第二电连接。 肖特基二极管可减少体二极管内的电荷积聚和第一功率MOSFET的反向恢复时间。 功率MOSFET和集成肖特基可用于电源转换或音频放大器电路。

公开(公告)号：US20090014791A1

公开(公告)日：2009-01-15

申请号：US12169349

申请日：2008-07-08

申请人： Samuel J. Anderson ,  David N. Okada ,  Gary Dashney ,  David A. Shumate

发明人： Samuel J. Anderson ,  David N. Okada ,  Gary Dashney ,  David A. Shumate

IPC分类号： H01L27/06 ,  H01L21/8234

CPC分类号： H01L29/7835 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/0619 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/66143 ,  H01L29/66659 ,  H01L29/872 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05572 ,  H01L2924/0002 ,  H01L2924/12032 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/05552

摘要： A semiconductor device includes a substrate. The substrate includes a semiconductor material. An electrically isolated region is formed over the substrate. A metal-oxide-semiconductor field-effect transistor (MOSFET) is formed over the substrate within the electrically isolated region. The electrically isolated region includes a trench formed around the electrically isolated region. An insulative material such as silicon dioxide (SiO2) may be deposited into the trench. A diode is formed over the substrate within the electrically isolated region. In one embodiment, the diode is a Schottky diode. A metal layer may be formed over a surface of the substrate to form an anode of the diode. A first electrical connection is formed between a source of the MOSFET and an anode of the diode. A second electrical connection is formed between a drain of the MOSFET and a cathode of the diode.

摘要翻译： 半导体器件包括衬底。 基板包括半导体材料。 在衬底上方形成电隔离区域。 在电隔离区域内的衬底上形成金属氧化物半导体场效应晶体管（MOSFET）。 电隔离区域包括围绕电隔离区域形成的沟槽。 可以将诸如二氧化硅（SiO 2）的绝缘材料沉积到沟槽中。 在电隔离区域内的衬底上形成二极管。 在一个实施例中，二极管是肖特基二极管。 可以在衬底的表面上形成金属层以形成二极管的阳极。 在MOSFET的源极和二极管的阳极之间形成第一电连接。 在MOSFET的漏极和二极管的阴极之间形成第二电连接。

公开(公告)号：US08895430B2

公开(公告)日：2014-11-25

申请号：US13434660

申请日：2012-03-29

申请人： Samuel J. Anderson ,  Gary Dashney ,  David N. Okada

发明人： Samuel J. Anderson ,  Gary Dashney ,  David N. Okada

IPC分类号： H01L21/44 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L24/11 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/03 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13014 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2924/00

摘要： A semiconductor device has a semiconductor wafer with a plurality of semiconductor die including a plurality of contact pads. An insulating layer is formed over the semiconductor wafer and contact pads. An under bump metallization (UBM) is formed over and electrically connected to the plurality of contact pads. A mask is disposed over the semiconductor wafer with a plurality of openings aligned over the plurality of contact pads. A conductive bump material is deposited within the plurality of openings in the mask and onto the UBM. The mask is removed. The conductive bump material is reflowed to form a plurality of bumps with a height less than a width. The plurality of semiconductor die is singulated. A singulated semiconductor die is mounted to a substrate with bumps oriented toward the substrate. Encapsulant is deposited over the substrate and around the singulated semiconductor die.

摘要翻译： 半导体器件具有带有多个具有多个接触焊盘的多个半导体管芯的半导体晶片。 在半导体晶片和接触焊盘之上形成绝缘层。 凹凸金属化（UBM）形成在多个接触焊盘上并电连接到多个接触焊盘。 掩模设置在半导体晶片上方，多个开口对准在多个接触焊盘上。 导电凸块材料沉积在掩模中的多个开口内并且沉积到UBM上。 去除面具。 导电凸块材料回流以形成高度小于宽度的多个凸块。 多个半导体管芯被切割。 将单片半导体管芯安装到具有朝向衬底的凸起的衬底上。 封装剂沉积在衬底上并围绕单片半导体管芯。

公开(公告)号：US20120248601A1

公开(公告)日：2012-10-04

申请号：US13434660

申请日：2012-03-29

申请人： Samuel J. Anderson ,  Gary Dashney ,  David N. Okada

发明人： Samuel J. Anderson ,  Gary Dashney ,  David N. Okada

IPC分类号： H01L23/498 ,  H01L21/78

CPC分类号： H01L24/11 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/03 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13014 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2924/00

摘要： A semiconductor device has a semiconductor wafer with a plurality of semiconductor die including a plurality of contact pads. An insulating layer is formed over the semiconductor wafer and contact pads. An under bump metallization (UBM) is formed over and electrically connected to the plurality of contact pads. A mask is disposed over the semiconductor wafer with a plurality of openings aligned over the plurality of contact pads. A conductive bump material is deposited within the plurality of openings in the mask and onto the UBM. The mask is removed. The conductive bump material is reflowed to form a plurality of bumps with a height less than a width. The plurality of semiconductor die is singulated. A singulated semiconductor die is mounted to a substrate with bumps oriented toward the substrate. Encapsulant is deposited over the substrate and around the singulated semiconductor die.

摘要翻译： 半导体器件具有带有多个具有多个接触焊盘的多个半导体管芯的半导体晶片。 在半导体晶片和接触焊盘之上形成绝缘层。 凹凸金属化（UBM）形成在多个接触焊盘上并电连接到多个接触焊盘。 掩模设置在半导体晶片上方，多个开口对齐在多个接触焊盘上。 导电凸块材料沉积在掩模中的多个开口内并且沉积到UBM上。 去除面具。 导电凸块材料回流以形成高度小于宽度的多个凸块。 多个半导体管芯被切割。 将单片半导体管芯安装到具有朝向衬底的凸起的衬底上。 封装剂沉积在衬底上并围绕单片半导体管芯。

公开(公告)号：US20080111221A1

公开(公告)日：2008-05-15

申请号：US11935299

申请日：2007-11-05

申请人： Samuel J. Anderson ,  David N. Okada

发明人： Samuel J. Anderson ,  David N. Okada

IPC分类号： H01L23/495 ,  H01L21/00

CPC分类号： H01L23/49562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/7835 ,  H01L2224/04042 ,  H01L2224/05001 ,  H01L2224/05082 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48611 ,  H01L2224/48624 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/49107 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： A power MOSFET is provided on a semiconductor die to withstand radiation exposure. The semiconductor die is mounted on a die flag of a leadframe. The MOSFET includes a substrate and epitaxial layer formed over the substrate. A source region is formed in a surface of the semiconductor die. The source region is coupled to the die flag. A contact pad is formed on the source region. A base region is formed in the surface of the semiconductor die adjacent to the source region. The base region is electrically connected to the contact pad. A drain region is formed in the surface of the semiconductor die. The drain region is coupled to a first wire bond pad on the leadframe. A gate structure is formed over a channel between the source region and drain region. The gate structure is coupled to a second wire bond pad on the leadframe.

摘要翻译： 在半导体管芯上提供功率MOSFET以承受辐射照射。 半导体管芯安装在引线框的管芯标记上。 MOSFET包括在衬底上形成的衬底和外延层。 源区域形成在半导体管芯的表面中。 源区域耦合到管芯标记。 在源极区域上形成接触焊盘。 在与源极区相邻的半导体管芯的表面形成有基极区域。 基极区域电连接到接触焊盘。 在半导体管芯的表面形成有漏极区域。 漏极区域耦合到引线框架上的第一引线接合焊盘。 在源极区和漏极区之间的沟道上形成栅极结构。 栅极结构耦合到引线框上的第二引线接合焊盘。

公开(公告)号：US09006099B2

公开(公告)日：2015-04-14

申请号：US13156281

申请日：2011-06-08

申请人： Samuel J. Anderson ,  David N. Okada

发明人： Samuel J. Anderson ,  David N. Okada

IPC分类号： H01L23/485 ,  H01L23/482 ,  H01L21/285 ,  H01L29/45 ,  H01L29/66 ,  H01L21/768 ,  H01L29/78 ,  H01L23/00

CPC分类号： H01L23/485 ,  H01L21/28518 ,  H01L21/76895 ,  H01L23/4824 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L29/456 ,  H01L29/665 ,  H01L29/7835 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05094 ,  H01L2224/05096 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05558 ,  H01L2224/05562 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11312 ,  H01L2224/1132 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/01082 ,  H01L2924/00 ,  H01L2224/05552

摘要： A semiconductor device has a substrate with a source region and a drain region formed on the substrate. A silicide layer is disposed over the source region and drain region. A first interconnect layer is formed over the silicide layer and includes a first runner connected to the source region and second runner connected to the drain region. A second interconnect layer is formed over the first interconnect layer and includes a third runner connected to the first runner and a fourth runner connected to the second runner. An under bump metallization (UBM) is formed over and electrically connected to the second interconnect layer. A mask is disposed over the substrate with an opening in the mask aligned over the UBM. A conductive bump material is deposited within the opening in the mask. The mask is removed and the conductive bump material is reflowed to form a bump.

摘要翻译： 半导体器件具有在衬底上形成有源区和漏区的衬底。 硅化物层设置在源区和漏区上。 第一互连层形成在硅化物层之上，并且包括连接到源极区域的第一流道和连接到漏极区域的第二流道。 第二互连层形成在第一互连层之上，并且包括连接到第一流道的第三流道和连接到第二流道的第四流道。 凹凸金属化（UBM）形成在第二互连层上并电连接到第二互连层。 掩模设置在衬底上，掩模中的开口在UBM上对准。 导电凸块材料沉积在掩模的开口内。 去除掩模并且导电凸块材料回流以形成凸块。

公开(公告)号：US08921186B2

公开(公告)日：2014-12-30

申请号：US12467157

申请日：2009-05-15

申请人： Patrick M. Shea ,  Samuel J. Anderson ,  David N. Okada

发明人： Patrick M. Shea ,  Samuel J. Anderson ,  David N. Okada

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/10 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L23/00

CPC分类号： H01L29/7824 ,  H01L24/13 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41775 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13644 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12041 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

摘要： A semiconductor device has a buried oxide layer formed over a substrate. An active silicon layer is formed over the buried oxide layer. A drain region is formed in the active silicon layer. An LDD drift region is formed in the active silicon layer adjacent to the drain region. The drift region has a graded doping distribution. A co-implant region is formed in the active silicon. A source region is formed in the co-implant region. A shallow trench insulator is formed along a top surface of the LDD drift region. The shallow trench isolator has a length less than the LDD drift region. The shallow trench insulator terminates under the polysilicon gate and within the LDD drift region. A polysilicon gate is formed above the active silicon layer between the source region and LDD drift region and at least partially overlapping the shallow trench insulator.

摘要翻译： 半导体器件具有在衬底上形成的掩埋氧化物层。 在掩埋氧化物层上形成有源硅层。 在有源硅层中形成漏区。 在与漏极区相邻的有源硅层中形成LDD漂移区。 漂移区具有渐变的掺杂分布。 在有源硅中形成共注入区域。 在共植入区域中形成源区。 沿着LDD漂移区的顶表面形成浅沟槽绝缘体。 浅沟槽隔离器的长度小于LDD漂移区。 浅沟槽绝缘体终止于多晶硅栅极之下并在LDD漂移区内。 在源极区和LDD漂移区之间的有源硅层之上形成多晶硅栅极，并且至少部分地与浅沟槽绝缘体重叠。

公开(公告)号：US20120313147A1

公开(公告)日：2012-12-13

申请号：US13156281

申请日：2011-06-08

申请人： Samuel J. Anderson ,  David N. Okada

发明人： Samuel J. Anderson ,  David N. Okada

IPC分类号： H01L27/118 ,  H01L21/82

CPC分类号： H01L23/485 ,  H01L21/28518 ,  H01L21/76895 ,  H01L23/4824 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L29/456 ,  H01L29/665 ,  H01L29/7835 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05094 ,  H01L2224/05096 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05558 ,  H01L2224/05562 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11312 ,  H01L2224/1132 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/01082 ,  H01L2924/00 ,  H01L2224/05552

摘要： A semiconductor device has a substrate with a source region and a drain region formed on the substrate. A silicide layer is disposed over the source region and drain region. A first interconnect layer is formed over the silicide layer and includes a first runner connected to the source region and second runner connected to the drain region. A second interconnect layer is formed over the first interconnect layer and includes a third runner connected to the first runner and a fourth runner connected to the second runner. An under bump metallization (UBM) is formed over and electrically connected to the second interconnect layer. A mask is disposed over the substrate with an opening in the mask aligned over the UBM. A conductive bump material is deposited within the opening in the mask. The mask is removed and the conductive bump material is reflowed to form a bump.

摘要翻译： 半导体器件具有在衬底上形成有源区和漏区的衬底。 硅化物层设置在源区和漏区上。 第一互连层形成在硅化物层之上，并且包括连接到源极区域的第一流道和连接到漏极区域的第二流道。 第二互连层形成在第一互连层之上，并且包括连接到第一流道的第三流道和连接到第二流道的第四流道。 凹凸金属化（UBM）形成在第二互连层上并电连接到第二互连层。 掩模设置在衬底上，掩模中的开口在UBM上对准。 导电凸块材料沉积在掩模的开口内。 去除掩模并且导电凸块材料回流以形成凸块。