公开(公告)号：US06720533B2

公开(公告)日：2004-04-13

申请号：US10216913

申请日：2002-08-13

申请人： Gyeong-Su Keum ,  Hyung-Sik Hong ,  Chung-Hun Park ,  Eun-Seok Song ,  Jae-Han Park

发明人： Gyeong-Su Keum ,  Hyung-Sik Hong ,  Chung-Hun Park ,  Eun-Seok Song ,  Jae-Han Park

IPC分类号： F27D1100

CPC分类号： H01L21/67103 ,  H05B3/28 ,  H05B2203/013 ,  H05B2203/017

摘要： A heater assembly of a semiconductor device manufacturing apparatus minimizes a temperature difference between a peripheral portion and a central portion of the wafer being processed in the apparatus. The heater assembly includes a unitary resistive heating member in the form of a disc, heat blocks that divide the peripheral portion and central portion of the upper surface of the disc into respective heating sections, a support for supporting the heating member, and an electric power source for supplying electric current to the unitary heating member. The widths of the heating sections become greater towards the center of the heater, and thus the electrical resistance of the heater also increases in a direction towards the center of the heater. The power source for the heater includes a lead that extends from the bottom surface of the heater to a bottom portion of the heater support.

摘要翻译： 半导体器件制造装置的加热器组件使装置内正在处理的晶片的周边部分和中心部分之间的温度差最小化。 加热器组件包括盘形式的单一电阻加热构件，将盘的上表面的周边部分和中心部分分成相应加热部分的加热块，用于支撑加热构件的支撑件和电力 用于向单一加热构件提供电流的源。 加热部分的宽度朝着加热器的中心变大，因此加热器的电阻也朝向加热器中心的方向增加。 加热器的电源包括从加热器的底表面延伸到加热器支撑件的底部的引线。

公开(公告)号：US08143713B2

公开(公告)日：2012-03-27

申请号：US12662268

申请日：2010-04-08

申请人： Eun-Seok Song ,  YoungHoon Ro

发明人： Eun-Seok Song ,  YoungHoon Ro

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L27/10 ,  H01L29/73 ,  H01L29/40

CPC分类号： H01L23/49855 ,  H01L2224/48091 ,  H01L2224/48228 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

摘要： Provided is a chip-on-board package. The chip-on-board package may include a board, a grounding pad on a first surface of the board, the grounding pad including a body portion and at least one line portion, and at least two conductive pads on the first surface, the at least two conductive pads being arranged adjacent to the body portion. The at least one line portion may extend between the at least two conductive pads and the at least one line portion may have a narrower width than the at least two conductive pads.

摘要翻译： 提供了一个芯片组的封装。 板上芯片封装可以包括板，板的第一表面上的接地焊盘，接地焊盘包括主体部分和至少一个线部分，以及在第一表面上的至少两个导电焊盘， 至少两个导电焊盘被布置成与主体部分相邻。 所述至少一个线部分可以在所述至少两个导电焊盘之间延伸，并且所述至少一个线部分可以具有比所述至少两个导电焊盘窄的宽度。

公开(公告)号：US20100167423A1

公开(公告)日：2010-07-01

申请号：US12656680

申请日：2010-02-12

申请人： Se-Ho You ,  Ki-Won Choi ,  Eun-Seok Song

发明人： Se-Ho You ,  Ki-Won Choi ,  Eun-Seok Song

IPC分类号： H01L21/768 ,  H01L21/31

CPC分类号： H01L23/552 ,  H01L23/525 ,  H01L24/06 ,  H01L24/14 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05124 ,  H01L2224/05548 ,  H01L2224/056 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06102 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/14104 ,  H01L2224/14515 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/00014

摘要： A semiconductor package includes a semiconductor chip having first and second pads, a first insulation layer pattern formed on the semiconductor chip and having first and second openings that expose the first and the second pads, respectively, a first conductive layer pattern elongated along the first insulation layer pattern from the first pad, a first external terminal formed on the first conductive layer pattern, a second insulation layer pattern formed on the first conductive layer pattern and the first insulation layer pattern to expose the first external terminal and having a third opening in communication with the second opening, a second conductive layer pattern elongated along the second insulation layer pattern from the second pad, and a second external terminal formed on the second conductive layer pattern.

摘要翻译： 半导体封装包括具有第一和第二焊盘的半导体芯片，形成在半导体芯片上并具有分别暴露第一和第二焊盘的第一和第二开口的第一绝缘层图案，沿着第一绝缘体延伸的第一导电层图案 来自第一焊盘的第一绝缘层图案，形成在第一导电层图案上的第一外部端子，形成在第一导电层图案上的第二绝缘层图案和第一绝缘层图案，以暴露第一外部端子并具有第三开口 具有第二开口，沿着第二绝缘层图案从第二衬垫延伸的第二导电层图案，以及形成在第二导电层图案上的第二外部端子。

公开(公告)号：US07880286B2

公开(公告)日：2011-02-01

申请号：US12222986

申请日：2008-08-21

申请人： Si-Hoon Lee ,  Eun-Seok Song

发明人： Si-Hoon Lee ,  Eun-Seok Song

IPC分类号： H01L23/52

CPC分类号： H01L23/552 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/50 ,  H01L24/17 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H05K1/0216 ,  H05K1/113 ,  H05K1/189 ,  H05K2201/0715 ,  H05K2201/09318 ,  H01L2924/00 ,  H01L2224/05599

摘要： A chip-on-film package may include a tape wiring substrate, a semiconductor chip mounted on the tape wiring substrate, and a molding compound provided between the semiconductor chip and the tape wiring substrate. The tape wiring substrate may include a film having upper and lower surfaces. Vias may penetrate the film. An upper metal layer may be provided on the upper surface of the film and include input terminal patterns and/or output terminal patterns. The input terminal patterns may include ground terminal patterns and/or power terminal patterns. A lower metal layer may be provided on the lower surface of the film and include a ground layer and/or a power layer. The ground layer and the power layer may cover at least a chip mounting area.

摘要翻译： 胶片封装可以包括带布线基板，安装在带布线基板上的半导体芯片，以及设置在半导体芯片和带布线基板之间的模塑料。 带状布线基板可以包括具有上表面和下表面的膜。 通风口可能会穿透电影。 上层金属层可以设置在膜的上表面上并且包括输入端子图案和/或输出端子图案。 输入端子图案可以包括接地端子图案和/或电源端子图案。 下部金属层可以设置在膜的下表面上并且包括接地层和/或功率层。 接地层和功率层可以至少覆盖芯片安装区域。

公开(公告)号：US20090290320A1

公开(公告)日：2009-11-26

申请号：US12453720

申请日：2009-05-20

申请人： Eun-Seok Song

发明人： Eun-Seok Song

IPC分类号： H05K9/00 ,  H01L23/552 ,  H05K1/02

CPC分类号： H05K1/0233 ,  H01L23/552 ,  H01L2924/0002 ,  H05K1/0216 ,  H05K2201/086 ,  H05K2201/09718 ,  H05K2201/09781 ,  H01L2924/00

摘要： A structure for blocking electromagnetic interference (EMI) may include at least one electromagnetic wave inducing member and an electromagnetic wave filtering member. The at least one electromagnetic wave inducing member may be provided to an electronic device to induce an electromagnetic wave applied to the electronic device. The electromagnetic wave filtering member may be provided to the electronic device to filter the electromagnetic wave induced by the at least one electromagnetic wave inducing member. Thus, the electromagnetic wave filtering member may remove the electromagnetic wave concentrated on the at least one electromagnetic wave inducing member, so that the electromagnetic wave applied to the electronic device may be effectively removed. As a result, circuits in the electronic device may be protected from the EMI.

摘要翻译： 用于阻挡电磁干扰（EMI）的结构可以包括至少一个电磁波感应构件和电磁波滤波构件。 可以将至少一个电磁波感应构件提供给电子设备以引起施加到电子设备的电磁波。 电磁波滤波构件可以设置在电子设备中，以对由至少一个电磁波诱导构件所引起的电磁波进行滤波。 因此，电磁波滤波构件可以去除集中在至少一个电磁波感应构件上的电磁波，从而可以有效地去除施加到电子装置的电磁波。 因此，可以保护电子设备中的电路不受EMI影响。

公开(公告)号：US20080315437A1

公开(公告)日：2008-12-25

申请号：US12222986

申请日：2008-08-21

申请人： Si-Hoon Lee ,  Eun-Seok Song

发明人： Si-Hoon Lee ,  Eun-Seok Song

IPC分类号： H01L23/52

CPC分类号： H01L23/552 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/50 ,  H01L24/17 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H05K1/0216 ,  H05K1/113 ,  H05K1/189 ,  H05K2201/0715 ,  H05K2201/09318 ,  H01L2924/00 ,  H01L2224/05599

摘要： A chip-on-film package may include a tape wiring substrate, a semiconductor chip mounted on the tape wiring substrate, and a molding compound provided between the semiconductor chip and the tape wiring substrate. The tape wiring substrate may include a film having upper and lower surfaces. Vias may penetrate the film. An upper metal layer may be provided on the upper surface of the film and include input terminal patterns and/or output terminal patterns. The input terminal patterns may include ground terminal patterns and/or power terminal patterns. A lower metal layer may be provided on the lower surface of the film and include a ground layer and/or a power layer. The ground layer and the power layer may cover at least a chip mounting area.

公开(公告)号：US08084359B2

公开(公告)日：2011-12-27

申请号：US12656680

申请日：2010-02-12

申请人： Se-Ho You ,  Ki-Won Choi ,  Eun-Seok Song

发明人： Se-Ho You ,  Ki-Won Choi ,  Eun-Seok Song

IPC分类号： H01L21/4763

CPC分类号： H01L23/552 ,  H01L23/525 ,  H01L24/06 ,  H01L24/14 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05124 ,  H01L2224/05548 ,  H01L2224/056 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06102 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/14104 ,  H01L2224/14515 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/00014

摘要： A semiconductor package includes a semiconductor chip having first and second pads, a first insulation layer pattern formed on the semiconductor chip and having first and second openings that expose the first and the second pads, respectively, a first conductive layer pattern elongated along the first insulation layer pattern from the first pad, a first external terminal formed on the first conductive layer pattern, a second insulation layer pattern formed on the first conductive layer pattern and the first insulation layer pattern to expose the first external terminal and having a third opening in communication with the second opening, a second conductive layer pattern elongated along the second insulation layer pattern from the second pad, and a second external terminal formed on the second conductive layer pattern.

摘要翻译： 半导体封装包括具有第一和第二焊盘的半导体芯片，形成在半导体芯片上并具有分别暴露第一和第二焊盘的第一和第二开口的第一绝缘层图案，沿着第一绝缘体延伸的第一导电层图案 来自第一焊盘的第一绝缘层图案，形成在第一导电层图案上的第一外部端子，形成在第一导电层图案上的第二绝缘层图案和第一绝缘层图案，以暴露第一外部端子并具有第三开口 具有第二开口，沿着第二绝缘层图案从第二衬垫延伸的第二导电层图案，以及形成在第二导电层图案上的第二外部端子。

公开(公告)号：US07420270B2

公开(公告)日：2008-09-02

申请号：US11362882

申请日：2006-02-28

申请人： Si-Hoon Lee ,  Eun-Seok Song

发明人： Si-Hoon Lee ,  Eun-Seok Song

IPC分类号： H01L23/52

CPC分类号： H01L23/552 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/50 ,  H01L24/17 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H05K1/0216 ,  H05K1/113 ,  H05K1/189 ,  H05K2201/0715 ,  H05K2201/09318 ,  H01L2924/00 ,  H01L2224/05599

摘要： A chip-on-film package may include a tape wiring substrate, a semiconductor chip mounted on the tape wiring substrate, and a molding compound provided between the semiconductor chip and the tape wiring substrate. The tape wiring substrate may include a film having upper and lower surfaces. Vias may penetrate the film. An upper metal layer may be provided on the upper surface of the film and include input terminal patterns and/or output terminal patterns. The input terminal patterns may include ground terminal patterns and/or power terminal patterns. A lower metal layer may be provided on the lower surface of the film and include a ground layer and/or a power layer. The ground layer and the power layer may cover at least a chip mounting area.

摘要翻译： 胶片封装可以包括带布线基板，安装在带布线基板上的半导体芯片，以及设置在半导体芯片和带布线基板之间的模塑料。 带状布线基板可以包括具有上表面和下表面的膜。 通风口可能会穿透电影。 上层金属层可以设置在膜的上表面上并且包括输入端子图案和/或输出端子图案。 输入端子图案可以包括接地端子图案和/或电源端子图案。 下部金属层可以设置在膜的下表面上并且包括接地层和/或功率层。 接地层和功率层可以至少覆盖芯片安装区域。

公开(公告)号：US20060097730A1

公开(公告)日：2006-05-11

申请号：US10519414

申请日：2003-07-07

申请人： Jin-Bae Park ,  Yong-June Shin ,  Jong-Qwan Yook ,  Edward Powers ,  Eun-Seok Song ,  Joo-Won Kim ,  Tok-Son Choe ,  Seung-Hoon Sung

发明人： Jin-Bae Park ,  Yong-June Shin ,  Jong-Qwan Yook ,  Edward Powers ,  Eun-Seok Song ,  Joo-Won Kim ,  Tok-Son Choe ,  Seung-Hoon Sung

IPC分类号： G01R31/11

CPC分类号： G01R31/088 ,  G01R31/11

摘要： An apparatus and method for high-resolution reflectometry that operates simultaneously in both the time and frequency domains, utilizing time-frequency signal analysis and a chirp signal multiplied by a Gaussian time envelope. The Gaussian envelope provides time localization, while the chirp allows one to excite the system under test with a swept sinewave covering a frequency band of interest. High resolution in detection of the reflected signal is provided by a time-frequency cross correlation function. The high-accuracy localization of faults in a wire/cable can be achieved by measurement of time delay offset obtained from the frequency offset of the reflected signal. The apparatus enables one to execute an automated diagnostic procedure of a wire/cable under test by control of peripheral devices.

摘要翻译： 一种利用时频信号分析和啁啾信号乘以高斯时间包络的时域和频域同时工作的高分辨率反射测量装置和方法。 高斯包络提供时间定位，而啁啾允许人们用覆盖感兴趣频段的扫频正弦波激发被测系统。 通过时间 - 频率互相关函数提供检测反射信号的高分辨率。 电线/电缆故障的高精度定位可以通过测量从反射信号的频偏获得的时间延迟偏移来实现。 该装置使得能够通过外围设备的控制来执行被测电线/电缆的自动诊断程序。

公开(公告)号：US20060097365A1

公开(公告)日：2006-05-11

申请号：US11258672

申请日：2005-10-25

申请人： Eun-Seok Song ,  Hee-Seok Lee

发明人： Eun-Seok Song ,  Hee-Seok Lee

IPC分类号： H01L23/495

CPC分类号： H01L24/49 ,  H01L23/3128 ,  H01L23/50 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/16 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/85051 ,  H01L2224/85986 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/85186 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2224/4554

摘要： A semiconductor package features a ring-shaped silicon decoupling capacitor that reduces simultaneous switching noise. The decoupling capacitor is fabricated on a substrate from silicon using a wafer fabrication process and takes the form of an annular capacitive structure that extends around a periphery of a substrate-mounted integrated circuit (IC). The decoupling capacitor has a reduced thickness on or below a chip level and takes the place of a conventional power/ground ring. Therefore, the decoupling capacitor can be disposed within the package without increasing the thickness and the size of the package. The decoupling capacitor may be coupled to various power pins, allowing optimum wire bonding, shortened electrical connections, and reduced inductance. Bonding wires connected to the decoupling capacitor have higher specific resistance, lowering the peak of the resonance frequency and thereby reducing simultaneous switching noise.