公开(公告)号：US20060097365A1

公开(公告)日：2006-05-11

申请号：US11258672

申请日：2005-10-25

申请人： Eun-Seok Song ,  Hee-Seok Lee

发明人： Eun-Seok Song ,  Hee-Seok Lee

IPC分类号： H01L23/495

CPC分类号： H01L24/49 ,  H01L23/3128 ,  H01L23/50 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/16 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/85051 ,  H01L2224/85986 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/85186 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2224/4554

摘要： A semiconductor package features a ring-shaped silicon decoupling capacitor that reduces simultaneous switching noise. The decoupling capacitor is fabricated on a substrate from silicon using a wafer fabrication process and takes the form of an annular capacitive structure that extends around a periphery of a substrate-mounted integrated circuit (IC). The decoupling capacitor has a reduced thickness on or below a chip level and takes the place of a conventional power/ground ring. Therefore, the decoupling capacitor can be disposed within the package without increasing the thickness and the size of the package. The decoupling capacitor may be coupled to various power pins, allowing optimum wire bonding, shortened electrical connections, and reduced inductance. Bonding wires connected to the decoupling capacitor have higher specific resistance, lowering the peak of the resonance frequency and thereby reducing simultaneous switching noise.

公开(公告)号：US07489035B2

公开(公告)日：2009-02-10

申请号：US11258672

申请日：2005-10-25

申请人： Eun-Seok Song ,  Hee-Seok Lee

发明人： Eun-Seok Song ,  Hee-Seok Lee

IPC分类号： H01L23/34

CPC分类号： H01L24/49 ,  H01L23/3128 ,  H01L23/50 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/16 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/85051 ,  H01L2224/85986 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/85186 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2224/4554

摘要： A semiconductor package features a ring-shaped silicon decoupling capacitor that reduces simultaneous switching noise. The decoupling capacitor is fabricated on a substrate from silicon using a wafer fabrication process and takes the form of an annular capacitive structure that extends around a periphery of a substrate-mounted integrated circuit (IC). The decoupling capacitor has a reduced thickness on or below a chip level and takes the place of a conventional power/ground ring. Therefore, the decoupling capacitor can be disposed within the package without increasing the thickness and the size of the package. The decoupling capacitor may be coupled to various power pins, allowing optimum wire bonding, shortened electrical connections, and reduced inductance. Bonding wires connected to the decoupling capacitor have higher specific resistance, lowering the peak of the resonance frequency and thereby reducing simultaneous switching noise.

摘要翻译： 半导体封装具有环形硅去耦电容器，可减少同时开关噪声。 去耦电容器使用晶片制造工艺从硅制造在衬底上，并且采用围绕衬底安装的集成电路（IC）的周边延伸的环形电容结构的形式。 去耦电容器在芯片级别或以下具有减小的厚度，并代替常规的电源/接地环。 因此，去耦电容器可以设置在封装内而不增加封装的厚度和尺寸。 去耦电容器可以耦合到各种电源引脚，允许最佳的引线键合，缩短的电连接和减小的电感。 连接到去耦电容器的接合线具有较高的电阻率，降低谐振频率的峰值，从而降低同时开关噪声。

公开(公告)号：US09048808B2

公开(公告)日：2015-06-02

申请号：US13803308

申请日：2013-03-14

申请人： Jae-Jin Park ,  Hee-Seok Lee ,  Ji-Hwan Hyun ,  Kang-Yeop Choo

发明人： Jae-Jin Park ,  Hee-Seok Lee ,  Ji-Hwan Hyun ,  Kang-Yeop Choo

IPC分类号： H03H9/10 ,  H03H9/05

CPC分类号： H03H9/0542 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/15331 ,  H03H9/0547 ,  H03H9/1014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00011 ,  H01L2224/45099

摘要： A semiconductor package includes a package substrate; an integrated circuit chip formed on one surface of the package substrate; and a sealed quartz oscillator formed on at least one of an inside, one surface, and the other surface of the package substrate, wherein the sealed quartz oscillator includes a substrate, a quartz blank formed on one surface of the substrate, and a sealing cap covering at least one surface of the quartz blank and including metal.

摘要翻译： 半导体封装包括封装衬底; 形成在所述封装基板的一个表面上的集成电路芯片; 以及密封石英振荡器，其形成在所述封装基板的内表面和所述另一表面中的至少一个表面上，其中所述密封石英振荡器包括基板，形成在所述基板的一个表面上的石英片，以及密封盖 覆盖石英坯料的至少一个表面并且包括金属。

公开(公告)号：US20110304015A1

公开(公告)日：2011-12-15

申请号：US13115431

申请日：2011-05-25

申请人： Yong-hoon Kim ,  Hee-Seok Lee ,  Jin-ha Jeong

发明人： Yong-hoon Kim ,  Hee-Seok Lee ,  Jin-ha Jeong

IPC分类号： H01L23/552

CPC分类号： H01L23/552 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0652 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1617 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package includes a substrate in which a plurality of wires are formed; at least one semiconductor chip electrically connected to portions of the plurality of wires; and a shielding can mounted on the substrate, surrounding the at least one semiconductor chip, electrically connected to at least one wire of the plurality of wires and including a soft magnetic material. The semiconductor package can prevent or substantially reduce electromagnetic interference (EMI).

摘要翻译： 半导体封装包括其中形成有多根导线的基板; 至少一个半导体芯片电连接到多个导线的部分; 并且屏蔽可以安装在基板上，围绕至少一个半导体芯片，电连接到多根导线中的至少一根导线并且包括软磁性材料。 半导体封装可以防止或显着降低电磁干扰（EMI）。

公开(公告)号：US20110269698A1

公开(公告)日：2011-11-03

申请号：US12600830

申请日：2009-01-02

申请人： Chan Lee ,  Hyuk-Hwan Song ,  Hee-Seok Lee

发明人： Chan Lee ,  Hyuk-Hwan Song ,  Hee-Seok Lee

IPC分类号： A61K38/15 ,  A61P43/00 ,  C07K11/02 ,  A61P35/00 ,  C12N1/14 ,  C12P21/04

CPC分类号： C07K11/02 ,  A61K38/00 ,  A61K38/15 ,  C12P21/02 ,  C12R1/77

摘要： Disclosed is a Fusarium strain producing novel cyclic pentadepsipeptides which are of excellent multidrug resistance-reversing activity and inhibitory activity against cancer cells. Also, novel cyclic pentadepsipeptides are provided as active ingredients of the compositions useful in the treatment of cancer and diseases associated with multidrug resistance.

摘要翻译： 公开了一种产生新型环戊五肽的镰刀菌菌株，其具有优异的多药耐药逆转活性和对癌细胞的抑制活性。 另外，提供新的环状五缩水甘油肽作为可用于治疗癌症和与多药耐药相关的疾病的组合物的活性成分。

公开(公告)号：US07956452B2

公开(公告)日：2011-06-07

申请号：US12461639

申请日：2009-08-19

申请人： Yun-Seok Choi ,  Hee-Seok Lee ,  Kyoung-Sei Choi

发明人： Yun-Seok Choi ,  Hee-Seok Lee ,  Kyoung-Sei Choi

IPC分类号： H01L23/48

CPC分类号： H01L21/563 ,  H01L23/295 ,  H01L23/60 ,  H01L24/16 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： Flip chip packages and methods of manufacturing the same are provided, the flip chip packages may include a package substrate, a semiconductor chip, conductive bumps, a ground pattern and an underfilling layer. The semiconductor chip may be over the package substrate. The conductive bumps may be between the semiconductor chip and the package substrate to electrically connect the semiconductor chip and the package substrate with each other. The ground pattern may ground one of the package substrate and the semiconductor chip. The underfilling layer may be between the package substrate and the semiconductor chip to surround the conductive bumps. The underfilling layer may have a diode selectively located between the ground pattern and the conductive bumps by electrostatic electricity applied to the underfilling layer to protect the semiconductor chip from the electrostatic electricity.

摘要翻译： 提供了倒装芯片封装及其制造方法，倒装芯片封装可以包括封装衬底，半导体芯片，导电凸块，接地图案和底部填充层。 半导体芯片可以在封装衬底之上。 导电凸块可以在半导体芯片和封装基板之间，以将半导体芯片和封装基板彼此电连接。 接地图可以将封装衬底和半导体芯片之一接地。 底部填充层可以在封装衬底和半导体芯片之间以包围导电凸块。 底部填充层可以通过施加到底部填充层的静电来选择性地位于接地图案和导电凸块之间的二极管，以保护半导体芯片免受静电。

公开(公告)号：US07868462B2

公开(公告)日：2011-01-11

申请号：US11541779

申请日：2006-10-03

申请人： Yun-Seok Choi ,  Hee-Seok Lee

发明人： Yun-Seok Choi ,  Hee-Seok Lee

IPC分类号： H01L23/538

CPC分类号： H01L25/0657 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/5227 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/05001 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01Q9/27 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A semiconductor package comprises a package board and a plurality of semiconductor chips sequentially stacked on the package board. Each of the semiconductor chips comprises a semiconductor substrate and an open loop-shaped chip line formed on the semiconductor substrate. The open loop-shaped chip line has first and second end portions. The first and second end portions of the open loop-shaped chip lines are electrically connected to each other by connectors, and the connectors and the open loop-shaped chip lines constitute a spiral antenna.

摘要翻译： 半导体封装包括封装板和顺序堆叠在封装板上的多个半导体芯片。 每个半导体芯片包括半导体衬底和形成在半导体衬底上的开环形芯片线。 开环状的芯片线具有第一和第二端部。 开环状芯片线的第一和第二端部通过连接器彼此电连接，并且连接器和开环形芯片线构成螺旋形天线。

公开(公告)号：US07330084B2

公开(公告)日：2008-02-12

申请号：US11296769

申请日：2005-12-06

申请人： Hee-Seok Lee ,  Kyung-Lae Jang ,  Tae-Je Cho ,  Ki-Won Choi

发明人： Hee-Seok Lee ,  Kyung-Lae Jang ,  Tae-Je Cho ,  Ki-Won Choi

IPC分类号： H01P3/08

CPC分类号： H01P3/003 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48095 ,  H01L2224/4917 ,  H01L2224/49175 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/19107 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/3025 ,  H01P3/08 ,  H05K1/0219 ,  H05K3/222 ,  H05K2201/09236 ,  H05K2203/049 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/00 ,  H01L2924/013 ,  H01L2924/00013

摘要： A printed circuit board for a high-speed semiconductor package uses bonding wires as a shield structure, e.g., to shield an open portion of signal transmission lines, and thereby reduce the likelihood of coupling noises, e.g., between signal transmission lines.

摘要翻译： 用于高速半导体封装的印刷电路板使用接合线作为屏蔽结构，例如屏蔽信号传输线的开放部分，从而降低例如信号传输线之间耦合噪声的可能性。

公开(公告)号：US07327020B2

公开(公告)日：2008-02-05

申请号：US11033997

申请日：2005-01-13

申请人： Heung-Kyu Kwon ,  Hee-Seok Lee

发明人： Heung-Kyu Kwon ,  Hee-Seok Lee

IPC分类号： H01L23/02

CPC分类号： H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/16 ,  H01L29/0657 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4911 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01072 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10158 ,  H01L2924/10161 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/16153 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A multi-chip package, a semiconductor device used therein, and manufacturing method thereof are provided. The multi-chip package may include a substrate having a plurality of substrate bonding pads formed on an upper surface thereof, at least one first semiconductor chip mounted on the substrate, and at least one second semiconductor chip mounted on the substrate where the at least one first semiconductor chip may be mounted. The at least one second semiconductor chip may include at least one three-dimensional space so as to allow the at least one first semiconductor chip to be enclosed within the at least one three-dimensional space. The at least one three-dimensional space may be a cavity, a groove, or a combination thereof.

摘要翻译： 提供一种多芯片封装，其中使用的半导体器件及其制造方法。 多芯片封装可以包括具有形成在其上表面上的多个衬底焊盘的衬底，安装在衬底上的至少一个第一半导体芯片以及安装在衬底上的至少一个第二半导体芯片，其中至少一个 可以安装第一半导体芯片。 至少一个第二半导体芯片可以包括至少一个三维空间，以便允许至少一个第一半导体芯片封装在至少一个三维空间内。 所述至少一个三维空间可以是空腔，凹槽或其组合。

公开(公告)号：US08253228B2

公开(公告)日：2012-08-28

申请号：US13045103

申请日：2011-03-10

申请人： Yong-Hoon Kim ,  Byeong-Yeon Cho ,  Hee-Seok Lee

发明人： Yong-Hoon Kim ,  Byeong-Yeon Cho ,  Hee-Seok Lee

IPC分类号： H01L23/02

CPC分类号： H01L25/0657 ,  H01L24/73 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0652 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00012 ,  H01L2924/00

摘要： A package on package structure includes a lower package and an upper package. The lower package includes a first semiconductor chip disposed in a chip region of an upper surface of a first substrate. The upper package includes a second semiconductor chip disposed on an upper surface of a second substrate, and a decoupling capacitor disposed in an outer region of a lower surface of the second substrate. The lower surface of the second substrate opposes the upper surface of the second substrate and faces the upper surface of the first substrate. The plane area of the second substrate is larger than the plane area of the first substrate. The outer region of the lower surface of the second substrate extends beyond a periphery of the first substrate.

摘要翻译： 包装结构上的包装包括下包装和上包装。 下封装包括设置在第一基板的上表面的芯片区域中的第一半导体芯片。 上部封装包括设置在第二基板的上表面上的第二半导体芯片和设置在第二基板的下表面的外部区域中的去耦电容器。 第二基板的下表面与第二基板的上表面相对并且面向第一基板的上表面。 第二基板的平面面积大于第一基板的平面面积。 第二基板的下表面的外部区域延伸超出第一基板的周边。