公开(公告)号：US5998868A

公开(公告)日：1999-12-07

申请号：US18736

申请日：1998-02-04

申请人： H. Bernhard Pogge ,  Bijan Davari ,  Johann Greschner ,  Howard L. Kalter

发明人： H. Bernhard Pogge ,  Bijan Davari ,  Johann Greschner ,  Howard L. Kalter

IPC分类号： H01L21/762 ,  H01L21/98 ,  H01L23/13 ,  H01L25/065 ,  H01L29/06 ,  H01L29/04

CPC分类号： H01L25/50 ,  H01L21/7624 ,  H01L21/76264 ,  H01L23/13 ,  H01L24/24 ,  H01L24/82 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/13022 ,  H01L2224/24137 ,  H01L2224/73267 ,  H01L2224/81141 ,  H01L2224/83141 ,  H01L2224/97 ,  H01L29/0657 ,  H01L2924/01019 ,  H01L2924/01055 ,  H01L2924/10158 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15156 ,  H01L2924/15157 ,  H01L2924/15165

摘要： An integrated circuit package or arrangement includes a carrier having a surface topography of projections or recesses for supporting individual semiconductor circuit chips having conversely matching bottom surface topographies to permit self-aligned positioning of the chips on the carrier. Top faces of neighboring chips lie substantially in planes separated by a distance of greater than 0.0 .mu.m. The neighboring chips are separated by a gap G or spacing in a range of approximately 1 .mu.m

摘要翻译： 集成电路封装或布置包括具有用于支撑具有相反匹配的底表面形貌的各个半导体电路芯片的突起或凹槽的表面形貌的载体，以允许芯片在载体上的自对准定位。 相邻芯片的顶面基本上位于距离大于0.0μm的平面中。 相邻的芯片由间隙G分开，间距约为1μm〜约100μm。 金属互连设置在顶面和间隙之上。 优选地，互连在间隙上具有逐渐的斜率。

公开(公告)号：US6087199A

公开(公告)日：2000-07-11

申请号：US18737

申请日：1998-02-04

申请人： H. Bernhard Pogge ,  Bijan Davari ,  Johann Greschner ,  Howard L. Kalter

发明人： H. Bernhard Pogge ,  Bijan Davari ,  Johann Greschner ,  Howard L. Kalter

IPC分类号： H01L21/768 ,  H01L21/98 ,  H01L23/13 ,  H01L25/065 ,  H01L29/06 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L25/50 ,  H01L21/76838 ,  H01L23/13 ,  H01L24/24 ,  H01L24/82 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/13022 ,  H01L2224/18 ,  H01L2224/24137 ,  H01L2224/73267 ,  H01L2224/83141 ,  H01L2224/97 ,  H01L29/0657 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01055 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/10158 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15156 ,  H01L2924/15157 ,  H01L2924/15165 ,  H01L2924/3025

摘要： A method for fabricating an integrated circuit package or arrangement includes providing a carrier having a surface topography of projections or recesses for supporting individual semiconductor circuit chips having conversely matching bottom surface topographies to permit self-aligned positioning of the chip on the carrier. Chips are provided such that top faces of neighboring chips lie substantially in planes separated by a distance of greater than 0.0 .mu.m. The carrier is arranged and dimensioned such that the neighboring chips are separated by a gap G or spacing in a range of 1 .mu.m

摘要翻译： 一种用于制造集成电路封装或布置的方法包括提供具有用于支撑具有相反匹配的底表面形貌的各个半导体电路芯片的突起或凹槽的表面形貌的载体，以允许芯片在载体上的自对准定位。 设置芯片使得相邻芯片的顶面基本上位于大于0.0μm的距离上的平面中。 载体的布置和尺寸使得相邻的芯片由间隙G分隔开，或间隔在1μm×100μm的范围内。 在顶面和间隙上设有金属互连。 优选地，互连在间隙上具有逐渐的斜率。

公开(公告)号：US5814885A

公开(公告)日：1998-09-29

申请号：US848037

申请日：1997-04-28

申请人： H. Bernhard Pogge ,  Johann Greschner ,  Howard L. Kalter

发明人： H. Bernhard Pogge ,  Johann Greschner ,  Howard L. Kalter

IPC分类号： H01L23/13 ,  H01L29/06 ,  H01L29/04 ,  H01L23/06

CPC分类号： H01L24/95 ,  H01L23/13 ,  H01L29/0657 ,  H01L2224/83141 ,  H01L2224/95136 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/10158 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/3025

摘要： An integrated circuit package including a carrier having a surface topography of projections or recesses for supporting individual semiconductor circuit chips having a conversely matching bottom surface topography to permit self-aligned positioning of the chip on the carrier.

摘要翻译： 一种集成电路封装，包括具有用于支撑具有相反匹配的底表面形貌的各个半导体电路芯片的突起或凹槽的表面形貌的载体，以允许芯片在载体上的自对准定位。

公开(公告)号：US06730529B1

公开(公告)日：2004-05-04

申请号：US09236183

申请日：1999-01-25

申请人： Howard L. Kalter ,  H. Bernhard Pogge ,  George S. Prokop ,  Donald L. Wheater

发明人： Howard L. Kalter ,  H. Bernhard Pogge ,  George S. Prokop ,  Donald L. Wheater

IPC分类号： G01R3126

CPC分类号： H01L22/32 ,  G01R31/2884

摘要： Large area chip functionality is tested at an intermediate level in the manufacturing process. A process sequence is implemented in which a layer of insulator material is deposited over the chip. This layer is then processed to selectively open areas over existing vias which are to be used for chip level testing. The other vias remain covered with insulator. A sacrificial metal level is then deposited on the insulator layer and patterned to create adequately large test pad areas connected to exposed vias. This metal layer and the insulator layer covering the other buried vias are removed after testing to re-establish the full via set. As an extension to this basic test process, test circuits can be formed around or beside the chip to be tested in the kerf areas separating the chip from other chips on the semiconductor wafer. Connections to the test circuits is with a sacrificial metal layer over an insulator layer. The sacrificial metal layer and insulator layer are removed after testing. The test circuits are scribed off in the process of separating the chips after back end of line processing is completed.

摘要翻译： 大面积芯片功能在制造过程的中间级别进行测试。 实现了在芯片上沉积绝缘体材料层的工艺顺序。 然后将该层处理成选择性地打开将用于芯片级测试的现有通孔上的区域。 其他通孔仍然用绝缘体覆盖。 然后将牺牲金属水平沉积在绝缘体层上并图案化以产生连接到暴露的通孔的足够大的测试焊盘区域。 在测试之后，该金属层和覆盖另一埋孔的绝缘体层被重新建立完整的通孔。 作为这个基本测试过程的延伸，测试电路可以在将芯片与半导体晶片上的其他芯片分开的切口区域中围绕或测试芯片周围形成。 与测试电路的连接在绝缘体层上具有牺牲金属层。 测试后去除牺牲金属层和绝缘体层。 在线路处理后端完成之后分离芯片的过程中，划线测试电路。

公开(公告)号：US5899703A

公开(公告)日：1999-05-04

申请号：US827207

申请日：1997-03-28

申请人： Howard L. Kalter ,  H. Bernhard Pogge ,  George S. Prokop ,  Donald L. Wheater

发明人： Howard L. Kalter ,  H. Bernhard Pogge ,  George S. Prokop ,  Donald L. Wheater

IPC分类号： G01R31/28 ,  H01L23/58 ,  G01R31/26 ,  H01L21/66

CPC分类号： H01L22/32 ,  G01R31/2884

摘要： Large area chip functionality is tested at an intermediate level in the manufacturing process. A process sequence is implemented in which a layer of insulator material is deposited over the chip. This layer is then processed to selectively open areas over existing vias which are to be used for chip level testing. The other vias remain covered with insulator. A sacrificial metal level is then deposited on the insulator layer and patterned to create adequately large test pad areas connected to exposed vias. This metal layer and the insulator layer covering the other buried vias are removed after testing to re-establish the full via set. As an extension to this basic test process, test circuits can be formed around or beside the chip to be tested in the kerf areas separating the chip from other chips on the semiconductor wafer. Connections to the test circuits is with a sacrificial metal layer over an insulator layer. The sacrificial metal layer and insulator layer are removed after testing. The test circuits are scribed off in the process of separating the chips after back end of line processing is completed.

摘要翻译： 大面积芯片功能在制造过程的中间级别进行测试。 实现了在芯片上沉积绝缘体材料层的工艺顺序。 然后将该层处理成选择性地打开将用于芯片级测试的现有通孔上的区域。 其他通孔仍然用绝缘体覆盖。 然后将牺牲金属水平沉积在绝缘体层上并图案化以产生连接到暴露的通孔的足够大的测试焊盘区域。 在测试之后，该金属层和覆盖另一埋孔的绝缘体层被重新建立完整的通孔。 作为这个基本测试过程的延伸，测试电路可以在将芯片与半导体晶片上的其他芯片分开的切口区域中围绕或测试芯片周围形成。 与测试电路的连接在绝缘体层上具有牺牲金属层。 测试后去除牺牲金属层和绝缘体层。 在线路处理后端完成之后分离芯片的过程中，划线测试电路。

公开(公告)号：US5866443A

公开(公告)日：1999-02-02

申请号：US884074

申请日：1997-06-27

申请人： H. Bernhard Pogge ,  Johann Greschner ,  Howard Leo Kalter ,  Raymond James Rosner

发明人： H. Bernhard Pogge ,  Johann Greschner ,  Howard Leo Kalter ,  Raymond James Rosner

IPC分类号： H01L21/28 ,  H01L21/301 ,  H01L21/98 ,  H01L25/065 ,  H01L29/06 ,  H01L21/44

CPC分类号： H01L25/50 ,  H01L25/0655 ,  H01L29/0657 ,  H01L2924/0002

摘要： Disclosed is an integrated circuit configuration including a carrier having recesses for supporting individual semiconductor die units. The semiconductor die units and the carrier recesses have lithographically defined dimensions so as to enable precise alignment and a high level of integration.

摘要翻译： 公开了一种集成电路结构，其包括具有用于支撑各个半导体管芯单元的凹部的载体。 半导体管芯单元和载体凹槽具有光刻定义的尺寸，以便能够精确对准和高集成度。

公开(公告)号：US5770884A

公开(公告)日：1998-06-23

申请号：US497498

申请日：1995-06-30

申请人： H. Bernhard Pogge ,  Johann Greschner ,  Howard Leo Kalter ,  Raymond James Rosner

发明人： H. Bernhard Pogge ,  Johann Greschner ,  Howard Leo Kalter ,  Raymond James Rosner

IPC分类号： H01L21/28 ,  H01L21/301 ,  H01L21/98 ,  H01L25/065 ,  H01L29/06 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L25/50 ,  H01L25/0655 ,  H01L29/0657 ,  H01L2924/0002

摘要： Disclosed is an integrated circuit configuration including a carrier having recesses for supporting individual semiconductor die units. The semiconductor die units and the carrier recesses have lithographically defined dimensions so as to enable precise alignment and a high level of integration.

摘要翻译： 公开了一种集成电路结构，其包括具有用于支撑各个半导体管芯单元的凹部的载体。 半导体管芯单元和载体凹槽具有光刻定义的尺寸，以便能够精确对准和高集成度。

公开(公告)号：US06429045B1

公开(公告)日：2002-08-06

申请号：US09779215

申请日：2001-02-07

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  H. Bernhard Pogge ,  Edmund J. Sprogis ,  Steven H. Voldman

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  H. Bernhard Pogge ,  Edmund J. Sprogis ,  Steven H. Voldman

IPC分类号： H01L2144

CPC分类号： H01L29/0657 ,  H01L21/563 ,  H01L23/544 ,  H01L24/81 ,  H01L25/0655 ,  H01L2223/54473 ,  H01L2224/16 ,  H01L2224/73203 ,  H01L2224/81005 ,  H01L2224/81007 ,  H01L2224/81136 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10158 ,  Y10S438/928 ,  H01L2924/00012

摘要： A technique for fabricating precision aligned macros (PAMs) with reduced risk of electrostatic discharge damage and thermal damage. An electrical and thermal contact is provided through the back of the individual chips to a supporting silicon substrate. A conductive seed layer for electroplating is formed on a support substrate. A dielectric (preferably, a thermid) layer is formed on the seed layer. Vias are formed in the thermid layer and metal contacts are formed in the vias. The front faces of two or more chips are bonded onto the top surface of an alignment substrate, and the chips are aligned to the alignment substrate. The back faces of the chips are bonded to the metal contacts and thermid layer with heat and pressure. The alignment substrate is removed. The front faces of the chips are planarized. Finally, interconnect wiring is formed over the chips and thermid layer.

摘要翻译： 一种制造精密对准宏（PAM）的技术，降低了静电放电损伤和热损伤的风险。 通过单个芯片的背面提供电接触和热接触到支撑硅衬底。 用于电镀的导电种子层形成在支撑衬底上。 在种子层上形成电介质（优选为热）层。 通孔形成在热层中，金属触点形成在通孔中。 将两个以上的芯片的正面接合在取向基板的顶面上，将芯片与取向基板对准。 芯片的背面通过热和压力结合到金属触点和热层。 取出对准基板。 芯片的正面平面化。 最后，在芯片和热层上形成互连布线。

公开(公告)号：US6110806A

公开(公告)日：2000-08-29

申请号：US280798

申请日：1999-03-26

申请人： H. Bernhard Pogge

发明人： H. Bernhard Pogge

IPC分类号： H01L25/18 ,  H01L21/68 ,  H01L23/538 ,  H01L23/544 ,  H01L25/04 ,  H01L21/30 ,  H01L21/46

CPC分类号： H01L23/5389 ,  H01L21/6835 ,  H01L23/544 ,  H01L24/24 ,  H01L24/82 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2223/54473 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/18162 ,  Y10S438/975 ,  Y10S438/977

摘要： A method is described for fabricating a module having a chip attached to a carrier substrate, wherein a guide substrate transparent to ablation radiation is used. A removable layer is provided on a surface of the guide substrate. A first alignment guide is formed on the removable layer, and a second alignment guide is formed on a front surface of the chip. The chip is aligned to the guide substrate by contacting the second alignment guide to the first alignment guide; the chip is then attached to the guide substrate. The carrier substrate is attached to the chip at the back surface of the chip. The interface between the removable layer and the guide substrate is then ablated using radiation (typically laser radiation) transmitted through the guide substrate, thereby detaching the guide substrate. Thin films with metal interconnections may then be provided on the front surface of the chip.

摘要翻译： 描述了一种用于制造具有附接到载体基板的芯片的模块的方法，其中使用对消融辐射透明的引导基板。 在导向基板的表面上设置有可移除层。 第一对准引导件形成在可移除层上，第二对准引导件形成在芯片的前表面上。 通过使第二对准引导件与第一对准引导件相接触来将芯片对准引导基板; 然后将芯片附接到引导衬底。 载体基板在芯片的背面安装在芯片上。 然后使用通过引导基板传输的辐射（通常是激光辐射）来消除可去除层和引导基板之间的界面，从而分离引导基板。 然后可以在芯片的前表面上提供具有金属互连的薄膜。

公开(公告)号：US07564118B2

公开(公告)日：2009-07-21

申请号：US12114145

申请日：2008-05-02

申请人： H. Bernhard Pogge ,  Roy Yu ,  Chandrika Prasad ,  Chandrasekhar Narayan

发明人： H. Bernhard Pogge ,  Roy Yu ,  Chandrika Prasad ,  Chandrasekhar Narayan

IPC分类号： H01L29/40 ,  H01L23/52 ,  H01L23/48 ,  H01L21/44

CPC分类号： H01L24/10 ,  H01L21/6835 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/525 ,  H01L24/13 ,  H01L24/81 ,  H01L25/0652 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/06181 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2224/81005 ,  H01L2224/94 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01057 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

摘要： A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via. The substrate may comprise a chip having a device (e.g. DRAM) fabricated therein. The process therefore permits vertical integration with a second chip (e.g. a PE chip). The plate may be a wafer attached to the substrate using a vertical stud/via interconnection. The substrate and plate may each have devices fabricated therein, so that the process provides vertical wafer-level integration of the devices.

摘要翻译： 金属化特征形成在基板的顶表面中，并且处理板附接到基板。 然后将衬底在其底表面处变薄以暴露特征的底部，以形成导电通孔。 衬底可以包括具有在其中制造的器件（例如DRAM）的芯片。 因此，该过程允许与第二芯片（例如，PE芯片）的垂直集成。 板可以是使用垂直螺柱/通孔互连连接到基板的晶片。 衬底和板可以各自具有在其中制造的器件，使得该工艺提供器件的垂直晶片级集成。