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公开(公告)号：US4098452A
公开(公告)日：1978-07-04
申请号：US730646
申请日：1976-10-07
CPC分类号： H01L24/27 , B23K1/20 , B23K35/001 , B23K35/005 , H01L24/28 , H01L24/32 , H01L24/83 , B23K2035/008 , B23K2201/40 , H01L2224/29109 , H01L2224/29111 , H01L2224/29113 , H01L2224/29116 , H01L2224/8319 , H01L2224/83801 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01018 , H01L2924/01023 , H01L2924/01032 , H01L2924/01033 , H01L2924/0104 , H01L2924/01041 , H01L2924/01042 , H01L2924/01049 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/19041
摘要： A bond between a refractory metal or semiconductor and a ductile metal and a method for making the same includes forming a layer of a refractory metal wetting agent such as titanium on the refractory metal before bonding to allow wetting of the refractory metal by the ductile metal.
摘要翻译： 耐火金属或半导体与延性金属之间的接合及其制造方法包括在接合之前在难熔金属上形成难熔金属润湿剂层例如钛的层，以允许通过延性金属润湿难熔金属。
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公开(公告)号：US3990833A
公开(公告)日：1976-11-09
申请号：US617522
申请日：1975-09-29
申请人： Fred F. Holub , Nicholas Roman , Harold F. Webster
发明人： Fred F. Holub , Nicholas Roman , Harold F. Webster
CPC分类号： H01C7/00 , C08K3/26 , C08K5/098 , G03B15/0426 , G03B15/0442 , G03B15/0457 , H05K1/0293 , H05K2201/0112 , H05K2203/173
摘要： A photoflash unit is designed to have a plurality of lamps fired individually and in sequence and includes a plurality of switching devices capable of being easily activated by radiant energy generated during flashing of the lamps. Initially, the switches have a high resistance ("off" condition) and after being activated by radiation, they undergo a chemical change to a conductive state ("on" condition). The switches are prepared from compositions which impart improved shelf life to the switches under conditions of high relative humidity.
摘要翻译： 闪光灯单元被设计成具有多个单独地并且依次发光的灯，并且包括多个开关装置，能够通过在灯的闪烁期间产生的辐射能容易地激活。 最初，开关具有高电阻（“关闭”状态），并且在被辐射激活之后，它们经历化学变化到导通状态（“接通”状态）。 开关由在相对湿度高的条件下为开关提供更好的保质期的组合物制备。
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公开(公告)号：US4996116A
公开(公告)日：1991-02-26
申请号：US454547
申请日：1989-12-21
CPC分类号： B32B15/018 , H05K1/0306 , H05K3/38 , Y10T428/12576 , Y10T428/12611 , Y10T428/1266 , Y10T428/12833 , Y10T428/12868 , Y10T428/12875 , Y10T428/12889 , Y10T428/12903
摘要： A direct (metal-metal compound eutectic) bond process is improved by disposing a eutectic/substrate-wetting enhancement layer on the substrate prior to performing the direct bond process to bond a metal foil to the substrate. Where the metal is copper, the direct bond process is rendered more effective than prior art direct bond processes on alumina and beryllia and makes the direct bond process effective on tungsten, molybdenum and aluminum nitride, all of which were unusable with the prior art direct bond copper process. A variety of new, useful structures may be produced using this process. The eutectic/substrate-wetting enhancement layer is preferably a noble-like metal or includes a noble-like metal such as platinum, palladium and gold.
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公开(公告)号：US4796156A
公开(公告)日：1989-01-03
申请号：US128847
申请日：1987-12-04
申请人： Harold F. Webster
发明人： Harold F. Webster
IPC分类号： H01L21/60 , H01L23/04 , H01L23/057 , H01L23/367 , H05K3/32 , H05K7/20
CPC分类号： H01L24/81 , H01L23/04 , H01L23/057 , H01L23/367 , H01L23/3675 , H01L24/75 , H01L2224/75 , H01L2224/81801 , H01L2924/01029 , H01L2924/01032 , H01L2924/01076 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H05K3/325
摘要： A method of self packaging an integrated circuit chip (10) on a printed circuit board (14) where conductive leads (16) form an electrical connection with interconnect leads (12) on the printed circuit board (14). A centering frame (22) placed on the printed circuit board serves to align the leads (12 and 16). A cooling cap (34) which dissipates heat from the integrated circuit chip (10) is placed over the centering frame (22) and integrated circuit chip (10). In one embodiment, the leads (12 and 16) form a pressure fit and the cooling cap (34) forces the pressure-fit electrical connections. In another embodiment, the leads (12 and 16) make rubbing contact with each other.
摘要翻译： 一种在印刷电路板（14）上自动包装集成电路芯片（10）的方法，其中导电引线（16）与印刷电路板（14）上的互连引线（12）形成电连接。 放置在印刷电路板上的定心框架（22）用于对准引线（12和16）。 从集成电路芯片（10）散热的冷却帽（34）放置在定心框架（22）和集成电路芯片（10）的上方。 在一个实施例中，引线（12和16）形成压配合，并且冷却帽（34）迫使压配合电连接。 在另一个实施例中，引线（12和16）彼此进行摩擦接触。
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公开(公告)号：US4541035A
公开(公告)日：1985-09-10
申请号：US635697
申请日：1984-07-30
IPC分类号： H01L23/522 , H01L21/70 , H01L21/768 , H01L23/12 , H01L23/14 , H01L23/538 , H01L27/13 , H05K3/46 , H05K1/14
CPC分类号： H01L23/5383 , H01L23/147 , H01L2224/05554 , H01L2224/48091 , H01L2224/48227 , H01L24/48 , H01L2924/00014 , H01L2924/01014 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/12042 , H01L2924/3011
摘要： A silicon circuit board incorporates multiple levels of patterned conductors. First level upper and lower patterned conductors are situated on an insulation-coated, monocrystalline silicon substrate. Upper and lower, high resistivity, polycrystalline silicon layers, in turn, are situated on the first level upper and lower patterned conductors, respectively. Second level upper and lower patterned conductors are situated over the upper and lower polycrystalline silicon layers. Further levels of patterned conductors in the circuit board may be provided by iteratively forming on the board polycrystalline silicon layers and patterned conductors. Conducting feedthroughs in the circuit board provide electrical communication between various patterened conductors.
摘要翻译： 硅电路板结合了多层图案导体。 第一级上下图案导体位于绝缘涂覆的单晶硅衬底上。 上，下，高电阻率，多晶硅层又分别位于第一级上下图案导体上。 第二级上下图案导体位于上多晶硅层和下多晶硅层之上。 可以通过在板上多层硅层和图案化导体上迭代地形成电路板中的图案导体的进一步水平。 在电路板中进行馈通可以提供各种感应导体之间的电气通信。
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公开(公告)号：US5273203A
公开(公告)日：1993-12-28
申请号：US38418
申请日：1993-03-29
申请人： Harold F. Webster
发明人： Harold F. Webster
CPC分类号： H01L21/67138 , C04B37/025 , C04B37/026 , H01L23/49811 , H05K3/4046 , C04B2237/06 , C04B2237/09 , C04B2237/124 , C04B2237/126 , C04B2237/34 , C04B2237/343 , C04B2237/408 , C04B2237/54 , C04B2237/62 , C04B2237/704 , C04B2237/706 , C04B2237/708 , C04B2237/72 , C04B2237/84 , C04B2237/88 , H01L2924/0002 , H05K1/0306 , H05K2201/10303 , H05K3/3447
摘要： A hermetic seal is provided for a conductive feedthrough through a thin ceramic component by a platinum or palladium lead by sealing the gap between the lead and the ceramic with a copper-copper oxide eutectic. The lead may have a copper coating on it prior to and subsequent to formation of the copper-copper oxide eutectic.
摘要翻译： 通过使用铜铜氧化物共晶体密封引线和陶瓷之间的间隙，通过铂或钯引线通过薄陶瓷部件提供气密密封。 在形成铜 - 铜 - 氧化物共晶体之前和之后，引线可以在其上具有铜涂层。
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公开(公告)号：US4831497A
公开(公告)日：1989-05-16
申请号：US906105
申请日：1986-09-11
申请人： Harold F. Webster , John P. Quine
发明人： Harold F. Webster , John P. Quine
CPC分类号： H05K9/0039 , H05K1/0228 , H05K1/0237 , H05K2201/09236 , H05K2201/10689 , Y10T29/49124 , Y10T29/49155
摘要： A circuit assembly including a plurality of integrated circuit chips wherein electrical interconnections between chips at a relatively large distance from each other are accomplished by a conductor bus comprising a first section including conductors running adjacent and parallel to each other for a distance substantially equal to an integral number of half wavelengths of the base frequency of signals of the circuit and second sections including conductors which sharply diverge toward associated integrated circuit chips for electrical connection therewith.
摘要翻译： 一种包括多个集成电路芯片的电路组件，其中在彼此相对较大距离的芯片之间的电互连通过导体总线实现，导体总线包括第一部分，第一部分包括彼此相邻并平行的导体，距离基本上等于积分 电路和第二部分的信号的基本频率的半波长的数量包括与相关联的集成电路芯片急剧偏离的导体，用于与其电连接。
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公开(公告)号：US4370590A
公开(公告)日：1983-01-25
申请号：US190941
申请日：1980-09-25
申请人： Harold F. Webster
发明人： Harold F. Webster
CPC分类号： G11C13/048 , H01J29/44
摘要： A method for storing data in an archival memory semiconductor target by providing a masking layer of a conductive material on the surface of an insulative layer upon the top surface of a semiconductor substrate; the material layer is assigned a two-dimensional array of possible data storage sites. The masking layer at those storage sites at which a first binary value is to be stored, is melted; the selected material is one which, at the melting temperature thereof, does not wet the surface of the chosen insulator whereby apertures are formed by the writing electron beam in the masking layer, at energy levels insufficient to evaporate the masking material. The writing beam energy is reduced at the data sites at which data bits of the remaining binary value are to be stored, and does not melt the masking material thereat. The data stored in the target is read by sweeping an electron beam of relatively low energy across the array to induce a flow of current from the semiconductor substrate and of magnitude dependent upon the presence or absence of an aperture in the masking layer at the data site interrogated.
摘要翻译： 一种通过在半导体衬底的顶表面上在绝缘层的表面上提供导电材料的掩模层来将数据存储在归档存储器半导体靶中的方法; 材料层被分配为可能的数据存储位置的二维阵列。 在要存储第一二进制值的那些存储位置处的掩蔽层被熔化; 所选择的材料是在其熔化温度下不会湿润所选择的绝缘体的表面的材料，其中通过掩模层中的写入电子束形成孔，其能量水平不足以蒸发掩蔽材料。 在要存储剩余二进制值的数据位的数据位置减少写入光束能量，并且不会在其上融化掩模材料。 存储在目标中的数据通过扫描阵列上相对较低能量的电子束来读取，以引起来自半导体衬底的电流流动并且取决于在数据位置处的掩模层中存在或不存在孔径 讯问了
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公开(公告)号：US4287572A
公开(公告)日：1981-09-01
申请号：US68680
申请日：1979-08-22
申请人： Harold F. Webster
发明人： Harold F. Webster
CPC分类号： G11C13/048
摘要： A method for storing data in an archival memory semiconductor target by providing a masking layer of a conductive material on the surface of an insulative layer upon the top surface of a semiconductor substrate; the material layer is assigned a two-dimensional array of possible data storage sites. The masking layer at those storage sites at which a first binary value is to be stored, is melted; the selected material is one which, at the melting temperature thereof, does not wet the surface of the chosen insulator whereby apertures are formed by the writing electron beam in the masking layer, at energy levels insufficient to evaporate the masking material. The writing beam energy is reduced at the data sites at which data bits of the remaining binary value are to be stored, and does not melt the masking material thereat. The data stored in the target is read by sweeping an electron beam of relatively low energy across the array to induce a flow of current from the semiconductor substrate and of magnitude dependent upon the presence or absence of an aperture in the masking layer at the data site interrogated.
摘要翻译： 一种通过在半导体衬底的顶表面上在绝缘层的表面上提供导电材料的掩模层来将数据存储在归档存储器半导体靶中的方法; 材料层被分配为可能的数据存储位置的二维阵列。 在要存储第一二进制值的那些存储位置处的掩蔽层被熔化; 所选择的材料是在其熔化温度下不会湿润所选择的绝缘体的表面的材料，其中通过掩模层中的写入电子束形成孔，其能量水平不足以蒸发掩蔽材料。 在要存储剩余二进制值的数据位的数据位置减少写入光束能量，并且不会在其上融化掩模材料。 存储在目标中的数据通过扫描阵列上相对较低能量的电子束来读取，以引起来自半导体衬底的电流流动并且取决于在数据位置处的掩模层中存在或不存在孔径 讯问了
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公开(公告)号：US4914812A
公开(公告)日：1990-04-10
申请号：US312849
申请日：1989-02-17
申请人： Harold F. Webster
发明人： Harold F. Webster
IPC分类号： H01L21/60 , H01L23/04 , H01L23/057 , H01L23/367 , H05K3/32
CPC分类号： H01L24/81 , H01L23/04 , H01L23/057 , H01L23/367 , H01L23/3675 , H01L2224/81801 , H01L2924/01029 , H01L2924/01032 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H05K3/325 , Y10T29/49128 , Y10T29/4913 , Y10T29/49146
摘要： A method of self packaging an integrated circuit chip on a printed circuit board where conductive leads form an electrical connection with interconnect leads on the printed circuit board. A centering frame placed on the printed circuit board serves to align the leads. A cooling cap which dissipates heat from the integrated circuit chip is placed over the centering frame and integrated circuit chip. In one embodiment, the leads form a pressure fit and the cooling cap forces the pressure-fit electrical connections. In another embodiment, the leads make rubbing contact with each other.
摘要翻译： 在印刷电路板上自动封装集成电路芯片的方法，其中导电引线与印刷电路板上的互连引线形成电连接。 放置在印刷电路板上的定心框用于对齐引线。 从集成电路芯片散热的冷却盖放置在定心框架和集成电路芯片上。 在一个实施例中，引线形成压配合，并且冷却帽迫使压配合电连接。 在另一个实施例中，引线彼此摩擦接触。
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