公开(公告)号：US06664176B2

公开(公告)日：2003-12-16

申请号：US09944796

申请日：2001-08-31

申请人： Harry Hedler ,  Thorsten Meyer ,  Stefan Ruckmich ,  Barbara Vasquez

发明人： Harry Hedler ,  Thorsten Meyer ,  Stefan Ruckmich ,  Barbara Vasquez

IPC分类号： H01L2144

CPC分类号： H01L24/12 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/06 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01068 ,  H01L2924/01072 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/19043

摘要： A method for forming printed re-routing for wafer level packaging, especially chip size packaging. The method includes forming a contact layer on a semiconductor die, printing a conductive redistribution structure on the contact layer, and etching the contact layer of the die by using the conductive redistribution structure as a self-aligning mask.

摘要翻译： 用于形成用于晶片级封装的印刷重新布线的方法，特别是芯片尺寸封装。 该方法包括在半导体管芯上形成接触层，在接触层上印刷导电再分布结构，并通过使用导电再分布结构作为自对准掩模来蚀刻管芯的接触层。

公开(公告)号：US06714418B2

公开(公告)日：2004-03-30

申请号：US10285924

申请日：2002-11-01

申请人： Gerd Frankowsky ,  Harry Hedler ,  Roland Irsigler ,  Thorsten Meyer ,  Barbara Vasquez

发明人： Gerd Frankowsky ,  Harry Hedler ,  Roland Irsigler ,  Thorsten Meyer ,  Barbara Vasquez

IPC分类号： H05K702

CPC分类号： H01L25/50 ,  H01L21/568 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L25/0657 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05573 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16237 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/15331 ,  H01L2924/00

摘要： An electronic component has a plurality of chips which are stacked one above the other and contact-connected to one another. To form this component, a first planar chip arrangement is provided with the functional chips spaced apart from one another in a grid and with a filling material in the spaces between the chips to form an insulating holding frame that fixes the chips, the frame has chip-dedicated contact-connecting elements that serve for the electrical contact-connection to another chip of another chip arrangement and each chip has dedicated electrically conductive strips. At least one additional planar chip arrangement is formed by the same method as the first planar chip arrangement and is then stacked on the first planar chip arrangement so that the two chip arrangements lie one above the other and the respective contact-connecting elements of the two chip arrangements are connected to one another for electrical chip-to-chip contact-connection. Subsequently, each of the components, which comprise a stack of chips, is separated from the assembled stack of chip arrangements.

摘要翻译： 电子部件具有多个彼此叠置并彼此接触连接的芯片。 为了形成该部件，第一平面芯片布置设置有功能芯片，其格栅彼此间隔开，并且在芯片之间的空间中具有填充材料，以形成固定芯片的绝缘保持框架，框架具有芯片 用于与另一个芯片布置的另一芯片的电接触连接的每个芯片具有专用的导电条。 通过与第一平面芯片布置相同的方法形成至少一个附加的平面芯片布置，然后将其堆叠在第一平面芯片布置上，使得两个芯片布置在另一个之上并且两个相应的触点连接元件 芯片布置彼此连接以进行电芯片到芯片的接触连接。 随后，包括一堆芯片的每个部件与组装的芯片布置堆叠分离。

公开(公告)号：US07087512B2

公开(公告)日：2006-08-08

申请号：US10642092

申请日：2003-08-15

申请人： Harry Hedler ,  Roland Irsigler ,  Thorsten Meyer ,  Barbara Vasquez

发明人： Harry Hedler ,  Roland Irsigler ,  Thorsten Meyer ,  Barbara Vasquez

IPC分类号： H01L21/44

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05026 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/05541 ,  H01L2224/05005 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166

摘要： A method for fabricating an integrated circuit connection region includes application of a dielectric to an integrated circuit with a connection region, application of a corrodible metalization layer to the dielectric, application of a protection device to the metalization layer, and removal of the protection device in a region around the connection region.

公开(公告)号：US06826037B2

公开(公告)日：2004-11-30

申请号：US10157175

申请日：2002-05-29

申请人： Harry Hedler ,  Thorsten Meyer ,  Barbara Vasquez

发明人： Harry Hedler ,  Thorsten Meyer ,  Barbara Vasquez

IPC分类号： H05K500

CPC分类号： H01L23/49816 ,  H01L23/13 ,  H01L23/49811 ,  H01L2924/0002 ,  H05K3/325 ,  H01L2924/00

摘要： An electronic structure includes an electronic component, which is configured to be in electric contact with a base and has a mounting side configured for mounting onto the base. The structure also includes a raised elastic support positioned on the component and multiple contacts positioned on the component, with at least one contact also being positioned on the support.

摘要翻译： 电子结构包括电子部件，其构造成与基座电接触，并且具有被配置为安装到基座上的安装侧。 该结构还包括定位在部件上的凸起弹性支撑件和位于部件上的多个触点，至少一个触点也位于支撑件上。

公开(公告)号：US20060244109A1

公开(公告)日：2006-11-02

申请号：US11383341

申请日：2006-05-15

申请人： Harry Hedler ,  Roland Irsigler ,  Thorsten Meyer ,  Barbara Vasquez

发明人： Harry Hedler ,  Roland Irsigler ,  Thorsten Meyer ,  Barbara Vasquez

IPC分类号： H01L23/495

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05026 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/05541 ,  H01L2224/05005 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166

摘要： A method for fabricating an integrated circuit connection region includes application of a dielectric to an integrated circuit with a connection region, application of a corrodible metalization layer to the dielectric, application of a protection device to the metalization layer, and removal of the protection device in a region around the connection region.

摘要翻译： 一种用于制造集成电路连接区域的方法包括将电介质施加到具有连接区域的集成电路，向电介质施加可腐蚀金属化层，向金属化层施加保护装置，以及将保护装置移除到 连接区域周围的区域。

公开(公告)号：US06845554B2

公开(公告)日：2005-01-25

申请号：US10298837

申请日：2002-11-18

申请人： Gerd Frankowsky ,  Harry Hedler ,  Roland Irsigler ,  Thorsten Meyer ,  Barbara Vasquez

发明人： Gerd Frankowsky ,  Harry Hedler ,  Roland Irsigler ,  Thorsten Meyer ,  Barbara Vasquez

IPC分类号： H01L21/00 ,  H01L21/60 ,  H01L21/78 ,  H05K3/30

CPC分类号： H01L24/96 ,  H01L21/67144 ,  H01L21/78 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16 ,  H01L2224/20 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0102 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49135 ,  Y10T29/49155 ,  Y10T29/53178

摘要： The invention creates a method for connection of circuit units (101a-10n) which are arranged on a wafer (100), in which the wafer (100) is fitted to a first film (102a), the wafer (100) is sawn such that the circuit units (101a-101n) which are arranged on the wafer (100) are separated, the functional circuit units (101d) are picked up by means of a handling device (101) and are placed down on a second film (102b) by means of the handling device (103), so as to produce a separation distance which can be predetermined between connection contacts of the circuit units (101d).

摘要翻译： 本发明创造了一种用于连接电路单元（101a-10n）的方法，它们布置在晶片（100）上，其中晶片（100）装配到第一薄膜（102a）上，晶片（100）被锯切 布置在晶片（100）上的电路单元（101a-101n）被分离，功能电路单元（101d）通过处理装置（101）拾取并放置在第二薄膜（102b）上 ），以便产生可以在电路单元（101d）的连接触点之间预定的间隔距离。

公开(公告)号：US20050250304A1

公开(公告)日：2005-11-10

申请号：US10642092

申请日：2003-08-15

申请人： Harry Hedler ,  Roland Irsigler ,  Thorsten Meyer ,  Barbara Vasquez

发明人： Harry Hedler ,  Roland Irsigler ,  Thorsten Meyer ,  Barbara Vasquez

IPC分类号： H01L21/60 ,  H01L23/485 ,  H01L21/44

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05026 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/05541 ,  H01L2224/05005 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166

摘要： A method for fabricating an integrated circuit connection region includes application of a dielectric to an integrated circuit with a connection region, application of a corrodible metalization layer to the dielectric, application of a protection device to the metalization layer, and removal of the protection device in a region around the connection region.

摘要翻译： 一种用于制造集成电路连接区域的方法包括将电介质施加到具有连接区域的集成电路，向电介质施加可腐蚀金属化层，向金属化层施加保护装置，以及将保护装置移除到 连接区域周围的区域。

公开(公告)号：US06905954B2

公开(公告)日：2005-06-14

申请号：US10634242

申请日：2003-08-05

申请人： Harry Hedler ,  Thorsten Meyer ,  Barbara Vasquez

发明人： Harry Hedler ,  Thorsten Meyer ,  Barbara Vasquez

IPC分类号： H01L21/60 ,  H01L23/485 ,  H01L23/498 ,  H01L21/44

CPC分类号： H01L24/12 ,  H01L23/498 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13006 ,  H01L2224/13099 ,  H01L2224/14051 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15747 ,  H01L2924/19043 ,  H01L2924/3011 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/00014

摘要： The present invention provides a method for producing a semiconductor device, with the steps of: applying an interconnect level (11, 12) to a semiconductor substrate (10); structuring the interconnect level (12); and applying a solder layer (13) on the structured interconnect level (11, 12) in such a way that the solder layer (13) assumes the structure of the interconnect level (11, 12). The present invention likewise provides such a semiconductor device.

摘要翻译： 本发明提供了一种制造半导体器件的方法，其特征在于包括：向半导体衬底（10）施加互连电平（11,12）。 构造互连级别（12）; 以及将所述焊料层（13）施加在所述结构化互连层（11,12）上，使得所述焊料层（13）呈现所述互连层（11,12）的结构。 本发明同样提供了这种半导体器件。

公开(公告)号：US07211451B2

公开(公告)日：2007-05-01

申请号：US10298772

申请日：2002-11-18

申请人： Thorsten Meyer ,  Gerd Frankowsky ,  Harry Hedler ,  Barbara Vasquez ,  Roland Irsigler

发明人： Thorsten Meyer ,  Gerd Frankowsky ,  Harry Hedler ,  Barbara Vasquez ,  Roland Irsigler

IPC分类号： H01L21/66 ,  H01L21/00 ,  H01L23/28 ,  H01L23/498

CPC分类号： H01L21/568 ,  H01L21/67121 ,  H01L21/67132 ,  H01L21/6835 ,  H01L22/20 ,  H01L23/3128 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/12105 ,  H01L2224/92 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2224/96 ,  H01L2224/82

摘要： A process for producing a component module comprising a module carrier and a plurality of components with which contact is made on the latter, comprising the following steps: arranging separated components on a surface-adhesive film at a predefined contact-specific spacing from one another, embedding the components in a flexible material in order to form a flexible holding frame which holds the components, pulling off the film, producing contact-making elements on the exposed side of the components, performing a functional test of the components and, if necessary, repair and/or replacement of components, and fixing and making contact with the components held in the holding frame on the module carrier.

摘要翻译： 一种用于制造组件模块的方法，所述组件模块包括模块载体和在其上形成接触的多个部件，包括以下步骤：以预定的接触特定间隔将表面粘合膜上的分离的组分布置在彼此之间， 将部件嵌入柔性材料中以形成保持部件的柔性保持框架，拉出膜，在部件的暴露侧上产生接触形成元件，执行部件的功能测试，并且如果需要， 修理和/或更换部件，以及固定和保持在模块架上的保持框架中保持的部件。

公开(公告)号：US06953708B2

公开(公告)日：2005-10-11

申请号：US10642063

申请日：2003-08-15

申请人： Harry Hedler ,  Thorsten Meyer ,  Barbara Vasquez

发明人： Harry Hedler ,  Thorsten Meyer ,  Barbara Vasquez

IPC分类号： H01L23/31 ,  H01L21/48

CPC分类号： H01L24/96 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3135 ,  H01L24/24 ,  H01L24/82 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05026 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05099

摘要： A method for producing a semiconductor component with the following steps. A semiconductor chip is provided having electrical contacts in a contact making region. A housing including a rear plate and a side area is provided and surrounds the semiconductor chip. A first compliant buffer layer is applied on a rear plate. The semiconductor chip is applied to the first compliant buffer layer, and a second compliant buffer layer is applied to and around the semiconductor chip except in the contact making region. A contact passage plate is provided with an opening over the contact areas and the contact passage plate is fixed to the second compliant buffer layer.

摘要翻译： 一种用于制造半导体部件的方法，其具有以下步骤。 在接触制造区域中提供具有电触点的半导体芯片。 提供包括后板和侧面区域的壳体并且围绕半导体芯片。 第一顺应性缓冲层被施加在后板上。 半导体芯片被施加到第一顺应性缓冲层，并且第二顺应性缓冲层被施加到半导体芯片之外并且在接触制造区域之外。 接触通道板在接触区域上设置有开口，并且接触通道板固定到第二柔顺缓冲层。