Nano structure electrode design
    9.
    发明申请
    Nano structure electrode design 有权
    纳米结构电极设计

    公开(公告)号:US20060278902A1

    公开(公告)日:2006-12-14

    申请号:US11270104

    申请日:2005-11-09

    IPC分类号: H01L29/76 H01L21/8234

    摘要: A microelectronic switch having a substrate layer, an electrically conductive switching layer formed on the substrate layer, an electrically conductive cavity layer formed on the switching layer, an electrically conductive cap layer formed on the cavity layer, the cap layer forming a first electrode and a second electrode that are physically and electrically separated one from another, and which both at least partially overlie the switching layer, and a cavity disposed between the switching layer and the second electrode, where the switching is layer is flexible to make electrical contact with the second electrode by flexing through the cavity upon selective application of an electrical bias.

    摘要翻译: 具有衬底层的微电子开关,形成在衬底层上的导电开关层,形成在开关层上的导电腔层,形成在腔层上的导电帽层,形成第一电极的帽层和 第二电极在物理上和电气上彼此分离,并且至少部分地覆盖在开关层上,并且设置在开关层和第二电极之间的空腔,其中开关层是柔性的,以与第二电极电接触 电极通过在选择性地施加电偏压时通过空腔弯曲。

    Self-aligned cell integration scheme
    10.
    发明申请
    Self-aligned cell integration scheme 失效
    自对准单元集成方案

    公开(公告)号:US20060281256A1

    公开(公告)日:2006-12-14

    申请号:US11312849

    申请日:2005-12-20

    IPC分类号: H01L21/336

    摘要: A method of forming a self-aligned logic cell. A nanotube layer is formed over the bottom electrode. A clamp layer is formed over the nanotube layer. The clamp layer covers the nanotube layer, thereby protecting the nanotube layer. A dielectric layer is formed over the clamp layer. The dielectric layer is etched. The clamp layer provides an etch stop and protects the nanotube layer. The clamp layer is etched with an isotropic etchant that etches the clamp layer underneath the dielectric layer, creating an overlap of the dielectric layer, and causing a self-alignment between the clamp layer and the dielectric layer. A spacer layer is formed over the nanotube layer. The spacer layer is etched except for a ring portion around the edge of the dielectric layer. The nanotube layer is etched except for portions that are underlying at least one of the clamp layer, the dielectric layer, and the spacer layer, thereby causing a self-alignment between the clamp layer, the overlap to the dielectric layer, the spacer layer, and the nanotube layer.

    摘要翻译: 一种形成自对准逻辑单元的方法。 在底部电极上形成纳米管层。 在纳米管层上形成夹层。 夹层覆盖纳米管层,从而保护纳米管层。 在钳位层上形成电介质层。 蚀刻介电层。 钳位层提供蚀刻停止并保护纳米管层。 用各向同性蚀刻剂蚀刻钳夹层,蚀刻介质层下方的夹层,产生电介质层的重叠,并引起钳位层和电介质层之间的自对准。 在纳米管层上形成间隔层。 除了围绕电介质层的边缘的环形部分之外,蚀刻间隔层。 除了夹持层,电介质层和间隔层中的至少一个的部分以外,蚀刻纳米管层,从而导致夹紧层之间的自对准,与电介质层的重叠,间隔层, 和纳米管层。