公开(公告)号：US20050032258A1

公开(公告)日：2005-02-10

申请号：US10854435

申请日：2004-05-27

申请人： Hiroshi Katagiri ,  Rokuro Kambe ,  Manabu Sato ,  Kazumasa Koike ,  Masaharu Seto ,  Takatoshi Suganuma ,  Akira Mizoguchi

发明人： Hiroshi Katagiri ,  Rokuro Kambe ,  Manabu Sato ,  Kazumasa Koike ,  Masaharu Seto ,  Takatoshi Suganuma ,  Akira Mizoguchi

IPC分类号： B32B15/08 ,  B28B1/30 ,  H05K1/03 ,  H05K3/00 ,  H05K3/40 ,  H05K3/46 ,  H01L21/00 ,  H01R43/00

CPC分类号： H05K3/4061 ,  H05K1/0306 ,  H05K3/0029 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2203/0152 ,  H05K2203/066 ,  Y10T29/49117 ,  Y10T29/49169 ,  Y10T29/49171

摘要： A carrier sheet for green sheet having a green sheet forming face on which a green sheet is to be formed, comprising: metal foil; and a resin film stacked on a first surface of said metal foil on a side of said green sheet forming face having a smaller thickness than that of said metal foil.

摘要翻译： 一种具有生坯片形成面的生片用载体片，其上形成有生片，包括：金属箔; 以及树脂膜，其在所述金属箔的第一表面上堆叠在所述生片形成面的与所述金属箔的厚度相比较小的一侧上。

公开(公告)号：US07259455B2

公开(公告)日：2007-08-21

申请号：US11075420

申请日：2005-03-09

申请人： Masaharu Seto

发明人： Masaharu Seto

IPC分类号： H01L23/12 ,  H01L23/28 ,  H01L23/29 ,  H01L21/00

CPC分类号： H01L23/562 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/3185 ,  H01L23/49816 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/14 ,  H01L2924/15321 ,  H01L2924/00012 ,  H01L2924/00

摘要： There is provided a semiconductor device including a semiconductor chip which includes a semiconductor substrate and a multilayer interconnection structure formed thereon, the multilayer interconnection structure including an interlayer insulating film smaller in relative dielectric constant than an SiO2 film, an encapsulating resin layer which covers a major surface of the semiconductor chip on a side of the multilayer interconnection structure and covers a side surface of the semiconductor chip, and a stress relaxing resin layer which is interposed between the semiconductor chip and the encapsulating resin layer, covers at least a part of an edge of the semiconductor chip on the side of the multilayer interconnection structure, and is smaller in Young's modulus than the encapsulating resin layer.

摘要翻译： 提供一种包括半导体芯片的半导体器件，其包括形成在其上的半导体衬底和多层互连结构，所述多层互连结构包括相对介电常数比SiO 2膜更小的层间绝缘膜， 封装树脂层，其覆盖所述多层互连结构侧的所述半导体芯片的主表面，并且覆盖所述半导体芯片的侧面;以及插入在所述半导体芯片和所述密封树脂层之间的应力缓和树脂层， 覆盖多层互连结构侧的半导体芯片的边缘的至少一部分，并且杨氏模量比封装树脂层小。

公开(公告)号：US20060189114A1

公开(公告)日：2006-08-24

申请号：US11358137

申请日：2006-02-22

申请人： Masaharu Seto ,  Hirokazu Ezawa

发明人： Masaharu Seto ,  Hirokazu Ezawa

IPC分类号： H01L21/50

CPC分类号： H01L24/13 ,  H01L23/525 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/023 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/11462 ,  H01L2224/11502 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/11901 ,  H01L2224/11906 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2924/0001 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2224/1146

摘要： According to an embodiment of the present invention, a method of manufacturing a semiconductor device, comprising forming a conducting layer on a substrate; forming a resist mask having an opening in a prescribed position on the conducting layer; forming a first plated film in the opening by supplying an electric current to the conducting layer; increasing the interval between an inner side surface of the resist mask forming the opening and the first plated film by setting back the inner side surface; and forming a second plated film in the opening resulting from the setback of the inner side surface to cover the first plated film by supplying an electric current to the conducting layer.

公开(公告)号：US20110049707A1

公开(公告)日：2011-03-03

申请号：US12850828

申请日：2010-08-05

申请人： Masaharu Seto ,  Soichi Yamashita ,  Hirokazu Ezawa

发明人： Masaharu Seto ,  Soichi Yamashita ,  Hirokazu Ezawa

IPC分类号： H01L23/485 ,  H01L21/768

CPC分类号： H01L24/11 ,  H01L21/76898 ,  H01L24/13 ,  H01L24/29 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/02311 ,  H01L2224/0391 ,  H01L2224/03912 ,  H01L2224/03916 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/1148 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/29011 ,  H01L2224/29022 ,  H01L2224/29034 ,  H01L2224/29076 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/73103 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/81815 ,  H01L2224/83193 ,  H01L2224/83201 ,  H01L2224/83855 ,  H01L2224/9211 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/0105 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/0132 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2924/00012

摘要： According to one embodiment, a semiconductor device includes an electrode pad, a protective layer, a bump, and a resin layer. The electrode pad is formed on a semiconductor substrate. The protective layer includes a pad opening formed in the position of the electrode pad. The bump is formed in the pad opening and electrically connected to the electrode pad. The resin layer has a space provided between the resin layer and the bump and is formed on the protective layer via a metal layer. The resin layer is formed by using an adhesive resin material.

摘要翻译： 根据一个实施例，半导体器件包括电极焊盘，保护层，凸块和树脂层。 电极焊盘形成在半导体衬底上。 保护层包括形成在电极焊盘的位置的焊盘开口。 凸块形成在焊盘开口中并电连接到电极焊盘。 树脂层具有设置在树脂层和凸块之间的空间，并通过金属层形成在保护层上。 树脂层通过使用粘合树脂材料形成。

公开(公告)号：US07473628B2

公开(公告)日：2009-01-06

申请号：US11358137

申请日：2006-02-22

申请人： Masaharu Seto ,  Hirokazu Ezawa

发明人： Masaharu Seto ,  Hirokazu Ezawa

IPC分类号： H01L21/44 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/13 ,  H01L23/525 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/023 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/11462 ,  H01L2224/11502 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/11901 ,  H01L2224/11906 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2924/0001 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2224/1146

摘要： According to an embodiment of the present invention, a method of manufacturing a semiconductor device, comprising forming a conducting layer on a substrate; forming a resist mask having an opening in a prescribed position on the conducting layer; forming a first plated film in the opening by supplying an electric current to the conducting layer; increasing the interval between an inner side surface of the resist mask forming the opening and the first plated film by setting back the inner side surface; and forming a second plated film in the opening resulting from the setback of the inner side surface to cover the first plated film by supplying an electric current to the conducting layer.

公开(公告)号：US5400210A

公开(公告)日：1995-03-21

申请号：US80107

申请日：1993-06-23

申请人： Noriyasu Sugimoto ,  Yukihiro Kimura ,  Masaharu Seto

发明人： Noriyasu Sugimoto ,  Yukihiro Kimura ,  Masaharu Seto

IPC分类号： H01B3/12 ,  H01G4/08 ,  H01G4/12 ,  H01L23/12 ,  H01L23/15 ,  H05K1/16 ,  H05K3/46 ,  H01G4/10

CPC分类号： H01G4/08

摘要： In a substrate having built-in capacitor which is incorporated in and united with an insulator, the capacitor has a dielectric layer made of a silicon nitride-based ceramic containing silicon carbide in an amount of from 13 to 30% by weight.

摘要翻译： 在具有内置电容器的衬底中，该绝缘体并入并结合在一起，该电容器具有由含有13至30重量％的碳化硅的氮化硅基陶瓷制成的电介质层。

公开(公告)号：US20090134516A1

公开(公告)日：2009-05-28

申请号：US12314135

申请日：2008-12-04

申请人： Masaharu Seto ,  Hirokazu Ezawa

发明人： Masaharu Seto ,  Hirokazu Ezawa

IPC分类号： H01L23/485

CPC分类号： H01L24/13 ,  H01L23/525 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/023 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/11462 ,  H01L2224/11502 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/11901 ,  H01L2224/11906 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2924/0001 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2224/1146

摘要： According to an embodiment of the present invention, a method of manufacturing a semiconductor device, comprising forming a conducting layer on a substrate; forming a resist mask having an opening in a prescribed position on the conducting layer; forming a first plated film in the opening by supplying an electric current to the conducting layer; increasing the interval between an inner side surface of the resist mask forming the opening and the first plated film by setting back the inner side surface; and forming a second plated film in the opening resulting from the setback of the inner side surface to cover the first plated film by supplying an electric current to the conducting layer.

摘要翻译： 根据本发明的实施例，一种制造半导体器件的方法，包括在衬底上形成导电层; 在所述导电层上形成具有规定位置的开口的抗蚀剂掩模; 通过向导电层提供电流在开口中形成第一镀膜; 通过设置内侧面来增加形成开口的抗蚀剂掩模的内侧表面与第一镀膜之间的间隔; 以及在所述开口中形成第二镀膜，所述第二镀膜通过向所述导电层提供电流而由所述内侧表面的挫折形成以覆盖所述第一镀膜。

公开(公告)号：US20050200022A1

公开(公告)日：2005-09-15

申请号：US11075420

申请日：2005-03-09

申请人： Masaharu Seto

发明人： Masaharu Seto

IPC分类号： H01L23/29 ,  H01L21/56 ,  H01L21/768 ,  H01L23/28 ,  H01L23/31 ,  H01L29/40

CPC分类号： H01L23/562 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/3185 ,  H01L23/49816 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/14 ,  H01L2924/15321 ,  H01L2924/00012 ,  H01L2924/00

摘要： There is provided a semiconductor device including a semiconductor chip which includes a semiconductor substrate and a multilayer interconnection structure formed thereon, the multilayer interconnection structure including an interlayer insulating film smaller in relative dielectric constant than an SiO2 film, an encapsulating resin layer which covers a major surface of the semiconductor chip on a side of the multilayer interconnection structure and covers a side surface of the semiconductor chip, and a stress relaxing resin layer which is interposed between the semiconductor chip and the encapsulating resin layer, covers at least a part of an edge of the semiconductor chip on the side of the multilayer interconnection structure, and is smaller in Young's modulus than the encapsulating resin layer.

摘要翻译： 提供一种包括半导体芯片的半导体器件，其包括形成在其上的半导体衬底和多层互连结构，所述多层互连结构包括相对介电常数比SiO 2膜更小的层间绝缘膜， 封装树脂层，其覆盖所述多层互连结构侧的所述半导体芯片的主表面，并且覆盖所述半导体芯片的侧面;以及插入在所述半导体芯片和所述密封树脂层之间的应力缓和树脂层， 覆盖多层互连结构侧的半导体芯片的边缘的至少一部分，并且杨氏模量比封装树脂层小。