公开(公告)号：US20110049707A1

公开(公告)日：2011-03-03

申请号：US12850828

申请日：2010-08-05

申请人： Masaharu Seto ,  Soichi Yamashita ,  Hirokazu Ezawa

发明人： Masaharu Seto ,  Soichi Yamashita ,  Hirokazu Ezawa

IPC分类号： H01L23/485 ,  H01L21/768

CPC分类号： H01L24/11 ,  H01L21/76898 ,  H01L24/13 ,  H01L24/29 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/02311 ,  H01L2224/0391 ,  H01L2224/03912 ,  H01L2224/03916 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/1148 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/29011 ,  H01L2224/29022 ,  H01L2224/29034 ,  H01L2224/29076 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/73103 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/81815 ,  H01L2224/83193 ,  H01L2224/83201 ,  H01L2224/83855 ,  H01L2224/9211 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/0105 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/0132 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2924/00012

摘要： According to one embodiment, a semiconductor device includes an electrode pad, a protective layer, a bump, and a resin layer. The electrode pad is formed on a semiconductor substrate. The protective layer includes a pad opening formed in the position of the electrode pad. The bump is formed in the pad opening and electrically connected to the electrode pad. The resin layer has a space provided between the resin layer and the bump and is formed on the protective layer via a metal layer. The resin layer is formed by using an adhesive resin material.

摘要翻译： 根据一个实施例，半导体器件包括电极焊盘，保护层，凸块和树脂层。 电极焊盘形成在半导体衬底上。 保护层包括形成在电极焊盘的位置的焊盘开口。 凸块形成在焊盘开口中并电连接到电极焊盘。 树脂层具有设置在树脂层和凸块之间的空间，并通过金属层形成在保护层上。 树脂层通过使用粘合树脂材料形成。

公开(公告)号：US20090134516A1

公开(公告)日：2009-05-28

申请号：US12314135

申请日：2008-12-04

申请人： Masaharu Seto ,  Hirokazu Ezawa

发明人： Masaharu Seto ,  Hirokazu Ezawa

IPC分类号： H01L23/485

CPC分类号： H01L24/13 ,  H01L23/525 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/023 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/11462 ,  H01L2224/11502 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/11901 ,  H01L2224/11906 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2924/0001 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2224/1146

摘要： According to an embodiment of the present invention, a method of manufacturing a semiconductor device, comprising forming a conducting layer on a substrate; forming a resist mask having an opening in a prescribed position on the conducting layer; forming a first plated film in the opening by supplying an electric current to the conducting layer; increasing the interval between an inner side surface of the resist mask forming the opening and the first plated film by setting back the inner side surface; and forming a second plated film in the opening resulting from the setback of the inner side surface to cover the first plated film by supplying an electric current to the conducting layer.

摘要翻译： 根据本发明的实施例，一种制造半导体器件的方法，包括在衬底上形成导电层; 在所述导电层上形成具有规定位置的开口的抗蚀剂掩模; 通过向导电层提供电流在开口中形成第一镀膜; 通过设置内侧面来增加形成开口的抗蚀剂掩模的内侧表面与第一镀膜之间的间隔; 以及在所述开口中形成第二镀膜，所述第二镀膜通过向所述导电层提供电流而由所述内侧表面的挫折形成以覆盖所述第一镀膜。

公开(公告)号：US08703600B2

公开(公告)日：2014-04-22

申请号：US12721741

申请日：2010-03-11

申请人： Tatsuo Migita ,  Hirokazu Ezawa ,  Soichi Yamashita ,  Takashi Togasaki

发明人： Tatsuo Migita ,  Hirokazu Ezawa ,  Soichi Yamashita ,  Takashi Togasaki

IPC分类号： H01L21/00 ,  H01L21/44

CPC分类号： H01L24/11 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05655 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06568 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/1306 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

摘要： An electronic component in which an element is formed on a chip includes: a pad that is made of a conductive material and that is formed in a first bump formation region that is two-dimensionally arranged in center of one principle face and in a second bump formation region that is linearly arranged at peripheral border of the principle face; a passivation film that is formed on the principle face to cover portion except a formation position of the pad; a metal layer that is formed on the pad; and a bump that is made of a conductive material and that is formed on the metal layer by plating, wherein radius of the metal layer in the second bump formation region is smaller than radius of at least some of the metal layer in the first bump formation region.

摘要翻译： 其中元件形成在芯片上的电子部件包括：由导电材料制成并且形成在二维布置在一个原理面的中心的第一凸块形成区域中的衬垫和在第二凸起 在原理面的周边边缘线性排列的形成区域; 钝化膜，其形成在除了所述焊盘的形成位置之外的所述原理面上以覆盖部分; 形成在所述垫上的金属层; 以及由导电材料制成并且通过电镀在金属层上形成的凸块，其中第二凸块形成区域中的金属层的半径小于第一凸块形成中的至少一些金属层的半径 地区。

公开(公告)号：US20060189114A1

公开(公告)日：2006-08-24

申请号：US11358137

申请日：2006-02-22

申请人： Masaharu Seto ,  Hirokazu Ezawa

发明人： Masaharu Seto ,  Hirokazu Ezawa

IPC分类号： H01L21/50

CPC分类号： H01L24/13 ,  H01L23/525 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/023 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/11462 ,  H01L2224/11502 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/11901 ,  H01L2224/11906 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2924/0001 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2224/1146

摘要： According to an embodiment of the present invention, a method of manufacturing a semiconductor device, comprising forming a conducting layer on a substrate; forming a resist mask having an opening in a prescribed position on the conducting layer; forming a first plated film in the opening by supplying an electric current to the conducting layer; increasing the interval between an inner side surface of the resist mask forming the opening and the first plated film by setting back the inner side surface; and forming a second plated film in the opening resulting from the setback of the inner side surface to cover the first plated film by supplying an electric current to the conducting layer.

公开(公告)号：US08314491B2

公开(公告)日：2012-11-20

申请号：US12845937

申请日：2010-07-29

申请人： Soichi Yamashita ,  Tatsuo Migita ,  Tadashi Iijima ,  Masahiro Miyata ,  Masayuki Uchida ,  Takashi Togasaki ,  Hirokazu Ezawa

发明人： Soichi Yamashita ,  Tatsuo Migita ,  Tadashi Iijima ,  Masahiro Miyata ,  Masayuki Uchida ,  Takashi Togasaki ,  Hirokazu Ezawa

IPC分类号： H01L23/48

CPC分类号： H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/16 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/02311 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05008 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05666 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13083 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/48666 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/81191 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45015 ,  H01L2924/207

摘要： According to one embodiment, a manufacturing method of a semiconductor device attained as follows. A dielectric layer having a first opening and a second opening reaching an electrode terminal is formed by modifying a photosensitive resin film on a substrate on which the electrode terminal of a first conductive layer is provided. Next, a second conductive layer that is electrically connected to the electrode terminal is formed on the dielectric layer that includes inside of the first opening, and a third conductive layer that has an oxidation-reduction potential of which difference from the oxidation-reduction potential of the first conductive layer is smaller than a difference of the oxidation-reduction potential between the first conductive layer and the second conductive layer is formed on the second conductive layer. Next, a dielectric layer having a third opening reaching the third conductive layer and a fourth opening reaching the electrode terminal via the second opening is formed by modifying a photosensitive resin film, and a bump that is electrically connected to the third conductive layer is formed.

摘要翻译： 根据一个实施例，半导体器件的制造方法如下。 通过改变在其上设置有第一导电层的电极端子的基板上的感光性树脂膜，形成具有第一开口和到达电极端子的第二开口的电介质层。 接下来，在包括第一开口的内部的电介质层上形成与电极端子电连接的第二导电层，以及具有与氧化还原电位不同的氧化还原电位的第三导电层 第一导电层小于在第二导电层上形成第一导电层和第二导电层之间的氧化还原电位的差异。 接下来，通过改变感光性树脂膜形成具有到达第三导电层的第三开口的电介质层和通过第二开口到达电极端子的第四开口，并且形成与第三导电层电连接的凸块。

公开(公告)号：US20100301472A1

公开(公告)日：2010-12-02

申请号：US12721741

申请日：2010-03-11

申请人： Tatsuo Migita ,  Hirokazu Ezawa ,  Soichi Yamashita ,  Takashi Togasaki

发明人： Tatsuo Migita ,  Hirokazu Ezawa ,  Soichi Yamashita ,  Takashi Togasaki

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L24/11 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05655 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06568 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/1306 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

摘要： An electronic component in which an element is formed on a chip includes: a pad that is made of a conductive material and that is formed in a first bump formation region that is two-dimensionally arranged in center of one principle face and in a second bump formation region that is linearly arranged at peripheral border of the principle face; a passivation film that is formed on the principle face to cover portion except a formation position of the pad; a metal layer that is formed on the pad; and a bump that is made of a conductive material and that is formed on the metal layer by plating, wherein radius of the metal layer in the second bump formation region is smaller than radius of at least some of the metal layer in the first bump formation region.

摘要翻译： 其中元件形成在芯片上的电子部件包括：由导电材料制成并且形成在二维布置在一个原理面的中心的第一凸块形成区域中的衬垫和在第二凸起 在原理面的周边边缘线性排列的形成区域; 钝化膜，其形成在除了所述焊盘的形成位置之外的所述原理面上以覆盖部分; 形成在所述垫上的金属层; 以及由导电材料制成并且通过电镀在金属层上形成的凸块，其中第二凸块形成区域中的金属层的半径小于第一凸块形成中的至少一些金属层的半径 地区。

公开(公告)号：US07473628B2

公开(公告)日：2009-01-06

申请号：US11358137

申请日：2006-02-22

申请人： Masaharu Seto ,  Hirokazu Ezawa

发明人： Masaharu Seto ,  Hirokazu Ezawa

IPC分类号： H01L21/44 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/13 ,  H01L23/525 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/023 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/11462 ,  H01L2224/11502 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/11901 ,  H01L2224/11906 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2924/0001 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2224/1146

摘要： According to an embodiment of the present invention, a method of manufacturing a semiconductor device, comprising forming a conducting layer on a substrate; forming a resist mask having an opening in a prescribed position on the conducting layer; forming a first plated film in the opening by supplying an electric current to the conducting layer; increasing the interval between an inner side surface of the resist mask forming the opening and the first plated film by setting back the inner side surface; and forming a second plated film in the opening resulting from the setback of the inner side surface to cover the first plated film by supplying an electric current to the conducting layer.

公开(公告)号：US09190373B2

公开(公告)日：2015-11-17

申请号：US13222332

申请日：2011-08-31

申请人： Tatsuo Migita ,  Hirokazu Ezawa ,  Soichi Yamashita ,  Masaya Shima

发明人： Tatsuo Migita ,  Hirokazu Ezawa ,  Soichi Yamashita ,  Masaya Shima

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31

CPC分类号： H01L24/11 ,  H01L21/76885 ,  H01L23/293 ,  H01L23/3157 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/0239 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05019 ,  H01L2224/05022 ,  H01L2224/05111 ,  H01L2224/05116 ,  H01L2224/05118 ,  H01L2224/05147 ,  H01L2224/05149 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13083 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/01028 ,  H01L2224/05552 ,  H01L2924/00

摘要： According to one embodiment, a semiconductor substrate, a redistribution trace, and a surface layer are provided, with the surface layer provided on the redistribution trace. On the semiconductor substrate, a wire and a pad electrode are formed. The redistribution trace is formed on the semiconductor substrate. The surface layer is larger in width than the redistribution trace, and extends beyond the edge of the redistribution trace.

摘要翻译： 根据一个实施例，提供半导体衬底，再分布迹线和表面层，其中所述表面层设置在再分布迹线上。 在半导体衬底上，形成导线和焊盘电极。 再分布痕迹形成在半导体衬底上。 表面层的宽度大于再分布迹线，并且延伸超出再分布迹线的边缘。

公开(公告)号：US20110024901A1

公开(公告)日：2011-02-03

申请号：US12845937

申请日：2010-07-29

申请人： Soichi Yamashita ,  Tatsuo Migita ,  Tadashi Iijima ,  Masahiro Miyata ,  Masayuki Uchida ,  Takashi Togasaki ,  Hirokazu Ezawa

发明人： Soichi Yamashita ,  Tatsuo Migita ,  Tadashi Iijima ,  Masahiro Miyata ,  Masayuki Uchida ,  Takashi Togasaki ,  Hirokazu Ezawa

IPC分类号： H01L23/52 ,  H01L21/283

CPC分类号： H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/16 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/02311 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05008 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05666 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13083 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/48666 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/81191 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45015 ,  H01L2924/207

摘要： According to one embodiment, a manufacturing method of a semiconductor device attained as follows. A dielectric layer having a first opening and a second opening reaching an electrode terminal is formed by modifying a photosensitive resin film on a substrate on which the electrode terminal of a first conductive layer is provided. Next, a second conductive layer that is electrically connected to the electrode terminal is formed on the dielectric layer that includes inside of the first opening, and a third conductive layer that has an oxidation-reduction potential of which difference from the oxidation-reduction potential of the first conductive layer is smaller than a difference of the oxidation-reduction potential between the first conductive layer and the second conductive layer is formed on the second conductive layer. Next, a dielectric layer having a third opening reaching the third conductive layer and a fourth opening reaching the electrode terminal via the second opening is formed by modifying a photosensitive resin film, and a bump that is electrically connected to the third conductive layer is formed.

摘要翻译： 根据一个实施例，半导体器件的制造方法如下。 通过改变在其上设置有第一导电层的电极端子的基板上的感光性树脂膜，形成具有第一开口和到达电极端子的第二开口的电介质层。 接下来，在包括第一开口的内部的电介质层上形成与电极端子电连接的第二导电层，以及具有与氧化还原电位不同的氧化还原电位的第三导电层 第一导电层小于在第二导电层上形成第一导电层和第二导电层之间的氧化还原电位的差异。 接下来，通过改变感光性树脂膜形成具有到达第三导电层的第三开口的电介质层和通过第二开口到达电极端子的第四开口，并且形成与第三导电层电连接的凸块。

公开(公告)号：US20120049367A1

公开(公告)日：2012-03-01

申请号：US13217746

申请日：2011-08-25

申请人： Tatsuo MIGITA ,  Hirokazu Ezawa ,  Soichi Yamashita

发明人： Tatsuo MIGITA ,  Hirokazu Ezawa ,  Soichi Yamashita

IPC分类号： H01L23/488 ,  H01L21/28

CPC分类号： H01L24/11 ,  H01L21/0206 ,  H01L21/0274 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11902 ,  H01L2224/13005 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/11 ,  H01L2924/2076 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2924/00

摘要： According to the embodiment, a pad electrode, a protective film, an under barrier metal film, and an electrode wiring portion are provided. The pad electrode is formed on a semiconductor substrate. The protective film is formed on the semiconductor substrate so that a surface of the pad electrode is exposed. The under barrier metal film is formed on the pad electrode and the protective film. The electrode wiring portion is formed on the pad electrode via the under barrier metal film. Moreover, a surface reflectance of the under barrier metal film is 30% or more at a wavelength of 800 nm, and a diameter of the electrode wiring portion is 140 μm or less.

摘要翻译： 根据本实施例，提供焊盘电极，保护膜，下阻挡金属膜和电极配线部。 焊盘电极形成在半导体衬底上。 保护膜形成在半导体基板上，使得焊盘电极的表面露出。 下阻挡金属膜形成在焊盘电极和保护膜上。 电极配线部通过下阻挡金属膜形成在焊盘电极上。 此外，在800nm波长下，下阻挡金属膜的表面反射率为30％以上，电极配线部的直径为140μm以下。