公开(公告)号：US20090134516A1

公开(公告)日：2009-05-28

申请号：US12314135

申请日：2008-12-04

申请人： Masaharu Seto ,  Hirokazu Ezawa

发明人： Masaharu Seto ,  Hirokazu Ezawa

IPC分类号： H01L23/485

CPC分类号： H01L24/13 ,  H01L23/525 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/023 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/11462 ,  H01L2224/11502 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/11901 ,  H01L2224/11906 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2924/0001 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2224/1146

摘要： According to an embodiment of the present invention, a method of manufacturing a semiconductor device, comprising forming a conducting layer on a substrate; forming a resist mask having an opening in a prescribed position on the conducting layer; forming a first plated film in the opening by supplying an electric current to the conducting layer; increasing the interval between an inner side surface of the resist mask forming the opening and the first plated film by setting back the inner side surface; and forming a second plated film in the opening resulting from the setback of the inner side surface to cover the first plated film by supplying an electric current to the conducting layer.

摘要翻译： 根据本发明的实施例，一种制造半导体器件的方法，包括在衬底上形成导电层; 在所述导电层上形成具有规定位置的开口的抗蚀剂掩模; 通过向导电层提供电流在开口中形成第一镀膜; 通过设置内侧面来增加形成开口的抗蚀剂掩模的内侧表面与第一镀膜之间的间隔; 以及在所述开口中形成第二镀膜，所述第二镀膜通过向所述导电层提供电流而由所述内侧表面的挫折形成以覆盖所述第一镀膜。

公开(公告)号：US20060189114A1

公开(公告)日：2006-08-24

申请号：US11358137

申请日：2006-02-22

申请人： Masaharu Seto ,  Hirokazu Ezawa

发明人： Masaharu Seto ,  Hirokazu Ezawa

IPC分类号： H01L21/50

CPC分类号： H01L24/13 ,  H01L23/525 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/023 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/11462 ,  H01L2224/11502 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/11901 ,  H01L2224/11906 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2924/0001 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2224/1146

摘要： According to an embodiment of the present invention, a method of manufacturing a semiconductor device, comprising forming a conducting layer on a substrate; forming a resist mask having an opening in a prescribed position on the conducting layer; forming a first plated film in the opening by supplying an electric current to the conducting layer; increasing the interval between an inner side surface of the resist mask forming the opening and the first plated film by setting back the inner side surface; and forming a second plated film in the opening resulting from the setback of the inner side surface to cover the first plated film by supplying an electric current to the conducting layer.

公开(公告)号：US20110049707A1

公开(公告)日：2011-03-03

申请号：US12850828

申请日：2010-08-05

申请人： Masaharu Seto ,  Soichi Yamashita ,  Hirokazu Ezawa

发明人： Masaharu Seto ,  Soichi Yamashita ,  Hirokazu Ezawa

IPC分类号： H01L23/485 ,  H01L21/768

CPC分类号： H01L24/11 ,  H01L21/76898 ,  H01L24/13 ,  H01L24/29 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/02311 ,  H01L2224/0391 ,  H01L2224/03912 ,  H01L2224/03916 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/1148 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/29011 ,  H01L2224/29022 ,  H01L2224/29034 ,  H01L2224/29076 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/73103 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/81815 ,  H01L2224/83193 ,  H01L2224/83201 ,  H01L2224/83855 ,  H01L2224/9211 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/0105 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/0132 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2924/00012

摘要： According to one embodiment, a semiconductor device includes an electrode pad, a protective layer, a bump, and a resin layer. The electrode pad is formed on a semiconductor substrate. The protective layer includes a pad opening formed in the position of the electrode pad. The bump is formed in the pad opening and electrically connected to the electrode pad. The resin layer has a space provided between the resin layer and the bump and is formed on the protective layer via a metal layer. The resin layer is formed by using an adhesive resin material.

摘要翻译： 根据一个实施例，半导体器件包括电极焊盘，保护层，凸块和树脂层。 电极焊盘形成在半导体衬底上。 保护层包括形成在电极焊盘的位置的焊盘开口。 凸块形成在焊盘开口中并电连接到电极焊盘。 树脂层具有设置在树脂层和凸块之间的空间，并通过金属层形成在保护层上。 树脂层通过使用粘合树脂材料形成。

公开(公告)号：US07473628B2

公开(公告)日：2009-01-06

申请号：US11358137

申请日：2006-02-22

申请人： Masaharu Seto ,  Hirokazu Ezawa

发明人： Masaharu Seto ,  Hirokazu Ezawa

IPC分类号： H01L21/44 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/13 ,  H01L23/525 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/023 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/11462 ,  H01L2224/11502 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/11901 ,  H01L2224/11906 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2924/0001 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2224/1146

摘要： According to an embodiment of the present invention, a method of manufacturing a semiconductor device, comprising forming a conducting layer on a substrate; forming a resist mask having an opening in a prescribed position on the conducting layer; forming a first plated film in the opening by supplying an electric current to the conducting layer; increasing the interval between an inner side surface of the resist mask forming the opening and the first plated film by setting back the inner side surface; and forming a second plated film in the opening resulting from the setback of the inner side surface to cover the first plated film by supplying an electric current to the conducting layer.

公开(公告)号：US08703600B2

公开(公告)日：2014-04-22

申请号：US12721741

申请日：2010-03-11

申请人： Tatsuo Migita ,  Hirokazu Ezawa ,  Soichi Yamashita ,  Takashi Togasaki

发明人： Tatsuo Migita ,  Hirokazu Ezawa ,  Soichi Yamashita ,  Takashi Togasaki

IPC分类号： H01L21/00 ,  H01L21/44

CPC分类号： H01L24/11 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05655 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06568 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/1306 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

摘要： An electronic component in which an element is formed on a chip includes: a pad that is made of a conductive material and that is formed in a first bump formation region that is two-dimensionally arranged in center of one principle face and in a second bump formation region that is linearly arranged at peripheral border of the principle face; a passivation film that is formed on the principle face to cover portion except a formation position of the pad; a metal layer that is formed on the pad; and a bump that is made of a conductive material and that is formed on the metal layer by plating, wherein radius of the metal layer in the second bump formation region is smaller than radius of at least some of the metal layer in the first bump formation region.

摘要翻译： 其中元件形成在芯片上的电子部件包括：由导电材料制成并且形成在二维布置在一个原理面的中心的第一凸块形成区域中的衬垫和在第二凸起 在原理面的周边边缘线性排列的形成区域; 钝化膜，其形成在除了所述焊盘的形成位置之外的所述原理面上以覆盖部分; 形成在所述垫上的金属层; 以及由导电材料制成并且通过电镀在金属层上形成的凸块，其中第二凸块形成区域中的金属层的半径小于第一凸块形成中的至少一些金属层的半径 地区。

公开(公告)号：US08063487B2

公开(公告)日：2011-11-22

申请号：US12335673

申请日：2008-12-16

申请人： Tatsuo Migita ,  Hirokazu Ezawa ,  Tadashi Iijima ,  Takashi Togasaki

发明人： Tatsuo Migita ,  Hirokazu Ezawa ,  Tadashi Iijima ,  Takashi Togasaki

IPC分类号： H01L23/48

CPC分类号： H01L23/525 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L24/81 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/13027 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06568 ,  H01L2924/0001 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/30105

摘要： A first conducting layer is formed on a side of a main surface on which an electrode terminal of a semiconductor device is provided in a semiconductor substrate. The first conducting layer is electrically connected to the electrode terminal of the semiconductor device. A mask layer that has an opening at a predetermined position is formed on the first conducting layer. A second conducting layer is formed inside the opening of the mask layer. The mask layer is removed. A relocation wiring that includes the first conducting layer and electrically draws out the electrode terminal is formed by performing anisotropic etching for the first conducting layer using the second conducting layer as a mask. Finally, a bump is formed on the relocation wiring by causing the second conducting layer to reflow.

摘要翻译： 第一导电层形成在半导体衬底中设置半导体器件的电极端子的主表面的一侧。 第一导电层电连接到半导体器件的电极端子。 在第一导电层上形成有在预定位置具有开口的掩模层。 在掩模层的开口内形成第二导电层。 去除掩模层。 通过使用第二导电层作为掩模对第一导电层进行各向异性蚀刻，形成包括第一导电层并电拔出电极端子的重定位布线。 最后，通过使第二导电层回流而在位移配线上形成凸点。

公开(公告)号：US07605076B2

公开(公告)日：2009-10-20

申请号：US11346236

申请日：2006-02-03

申请人： Makoto Honda ,  Kaori Yomogihara ,  Kazuhiro Murakami ,  Masanori Numano ,  Takahito Nagamatsu ,  Hideaki Harakawa ,  Hideto Matsuyama ,  Hirokazu Ezawa ,  Hisashi Kaneko

发明人： Makoto Honda ,  Kaori Yomogihara ,  Kazuhiro Murakami ,  Masanori Numano ,  Takahito Nagamatsu ,  Hideaki Harakawa ,  Hideto Matsuyama ,  Hirokazu Ezawa ,  Hisashi Kaneko

IPC分类号： H01L21/4763 ,  H01L21/28 ,  H01L21/302

CPC分类号： H01L21/76802 ,  H01L21/02063 ,  H01L21/31116 ,  H01L21/76814

摘要： An insulating film formed on a conducting layer is dry-etched so as to make a connection hole in the insulating film to expose the conducting layer. Plasma is supplied onto the exposed conducting layer to dry-clean a damage layer produced in the connection hole. A product produced in the connection hole as a result of the dry cleaning is removed by a wet process. An oxide film formed in the connection hole as a result of the wet process is etched by a chemical dry process using a gas including either NF3 or HF. A thermally decomposable reaction product produced as a result of the etching is removed by heat treatment.

摘要翻译： 对形成在导电层上的绝缘膜进行干蚀刻，以在绝缘膜上形成连接孔，使导电层露出。 将等离子体供应到暴露的导电层上以干燥在连接孔中产生的损伤层。 作为干式清洗的连接孔中产生的产品通过湿法除去。 通过使用包括NF 3或HF的气体的化学干法，蚀刻形成在连接孔中的作为湿法处理的结果的氧化膜。 通过热处理除去作为蚀刻结果产生的可热分解的反应产物。

公开(公告)号：US20060055050A1

公开(公告)日：2006-03-16

申请号：US11221762

申请日：2005-09-09

申请人： Hideo Numata ,  Hirokazu Ezawa ,  Chiaki Takubo ,  Kenji Takahashi ,  Hideo Aoki ,  Susumu Harada ,  Hisashi Kaneko ,  Hiroshi Ikenoue ,  Mie Matsuo ,  Ichiro Omura

发明人： Hideo Numata ,  Hirokazu Ezawa ,  Chiaki Takubo ,  Kenji Takahashi ,  Hideo Aoki ,  Susumu Harada ,  Hisashi Kaneko ,  Hiroshi Ikenoue ,  Mie Matsuo ,  Ichiro Omura

IPC分类号： H01L23/48

CPC分类号： H01L25/50 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05147 ,  H01L2224/05569 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/05599

摘要： A semiconductor device comprises a semiconductor substrate having an through hole, a first insulation resin layer formed on an inner surface of the through hole, a second insulation resin layer formed on at least one of front and rear surfaces of the semiconductor substrate, and a first conductor layer formed in the through hole to connect at least both front and rear surfaces of the semiconductor substrate and insulated from the inner surface of the through hole with the first insulation resin layer. A second conductor layer (wiring pattern) which is electrically connected to the first conductor layer in the through hole is further provided on the second insulation resin layer. The conductor layer formed in the through hole and constituting a connecting plug has a high insulation reliability. Therefore, a semiconductor device suitable for a multi-chip package and the like can be obtained. Further, since the forming ability of the conductor layer connecting the front and rear surfaces and the insulation layer is high, the manufacturing cost can be reduced.

摘要翻译： 半导体器件包括具有通孔的半导体衬底，形成在通孔的内表面上的第一绝缘树脂层，形成在半导体衬底的前后表面中的至少一个上的第二绝缘树脂层，以及第一绝缘树脂层 形成在所述通孔中的导体层至少连接半导体衬底的前表面和后表面，并与所述通孔的内表面与所述第一绝缘树脂层绝缘。 在第二绝缘树脂层上还设置有与通孔中的第一导体层电连接的第二导体层（布线图案）。 形成在通孔中并构成连接插头的导体层具有高的绝缘可靠性。 因此，可以获得适合于多芯片封装等的半导体器件。 此外，由于连接前后表面和绝缘层的导体层的形成能力高，所以可以降低制造成本。

公开(公告)号：US5529634A

公开(公告)日：1996-06-25

申请号：US424623

申请日：1995-04-19

申请人： Masahiro Miyata ,  Hidemitsu Egawa ,  Johta Fukuhara ,  Shinzi Takeda ,  Hirokazu Ezawa

发明人： Masahiro Miyata ,  Hidemitsu Egawa ,  Johta Fukuhara ,  Shinzi Takeda ,  Hirokazu Ezawa

IPC分类号： C23C14/04 ,  C23C14/22 ,  H01L21/60 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  C23C16/00

CPC分类号： C23C14/228 ,  C23C14/04 ,  C23C14/22 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/53242 ,  H01L24/11 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/3025

摘要： An evaporation chamber for forming fine metal particles is separated from a film formation chamber in which the substrate having a metal film such as a metal column thereon is placed during metal film deposition. The pressure of the film formation chamber is set to be lower than that of the evaporation chamber, and the fine metal particles are sprayed on the substrate by the pressure difference to form the metal column. Therefore, a wiring layer, a connection electrode for connecting the wiring layer to another wiring layer, and the like can easily be formed by a small number of steps.

摘要翻译： 用于形成细金属颗粒的蒸发室与成膜室分离，其中在金属膜沉积期间放置有金属膜如金属柱的金属膜的基板。 成膜室的压力被设定为低于蒸发室的压力，并且通过压力差将金属微粒喷射在基板上以形成金属柱。 因此，可以通过少量的步骤容易地形成布线层，用于将布线层连接到另一布线层的连接电极等。

公开(公告)号：US08569181B2

公开(公告)日：2013-10-29

申请号：US13267048

申请日：2011-10-06

申请人： Tatsuo Migita ,  Hirokazu Ezawa ,  Tadashi Iijima ,  Takashi Togasaki

发明人： Tatsuo Migita ,  Hirokazu Ezawa ,  Tadashi Iijima ,  Takashi Togasaki

IPC分类号： H01L21/461 ,  H01L21/38

CPC分类号： H01L23/525 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L24/81 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/13027 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06568 ,  H01L2924/0001 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/30105

摘要： A first conducting layer is formed on a side of a main surface on which an electrode terminal of a semiconductor device is provided in a semiconductor substrate. The first conducting layer is electrically connected to the electrode terminal of the semiconductor device. A mask layer that has an opening at a predetermined position is formed on the first conducting layer. A second conducting layer is formed inside the opening of the mask layer. The mask layer is removed. A relocation wiring that includes the first conducting layer and electrically draws out the electrode terminal is formed by performing anisotropic etching for the first conducting layer using the second conducting layer as a mask. Finally, a bump is formed on the relocation wiring by causing the second conducting layer to reflow.

摘要翻译： 第一导电层形成在半导体衬底中设置半导体器件的电极端子的主表面的一侧。 第一导电层电连接到半导体器件的电极端子。 在第一导电层上形成有在预定位置具有开口的掩模层。 在掩模层的开口内形成第二导电层。 去除掩模层。 通过使用第二导电层作为掩模对第一导电层进行各向异性蚀刻，形成包括第一导电层并电拔出电极端子的重定位布线。 最后，通过使第二导电层回流而在位移配线上形成凸点。