公开(公告)号：US06838748B2

公开(公告)日：2005-01-04

申请号：US10434205

申请日：2003-05-09

申请人： Toshiya Ishio ,  Hiroyuki Nakanishi ,  Katsunobu Mori ,  Yoshihide Iwazaki ,  Shinji Suminoe

发明人： Toshiya Ishio ,  Hiroyuki Nakanishi ,  Katsunobu Mori ,  Yoshihide Iwazaki ,  Shinji Suminoe

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/552 ,  H01L29/06

CPC分类号： H01L23/552 ,  H01L23/3114 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L29/0657 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10158 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor chip of the present invention is so arranged that a front face on which an element circuit is formed has electrode pads and a side face and a back face are coated with a shielding layer for shielding electromagnetic waves. With this, it is possible to provide a semiconductor element capable of being easily manufactured into a smaller semiconductor device compared with a conventional semiconductor device equipped with a shielding cap; a semiconductor device; and a method for manufacturing a semiconductor element.

摘要翻译： 本发明的半导体芯片被布置成使得其上形成有元件电路的正面具有电极焊盘，并且侧面和背面涂覆有用于屏蔽电磁波的屏蔽层。 由此，与配备有屏蔽盖的现有的半导体装置相比，可以提供能够容易地制造成较小的半导体装置的半导体元件; 半导体器件; 以及半导体元件的制造方法。

公开(公告)号：US20060237848A1

公开(公告)日：2006-10-26

申请号：US11474469

申请日：2006-06-26

申请人： Shinji Suminoe ,  Hiroyuki Nakanishi ,  Toshiya Ishio ,  Yoshihide Iwazaki ,  Katsunobu Mori

发明人： Shinji Suminoe ,  Hiroyuki Nakanishi ,  Toshiya Ishio ,  Yoshihide Iwazaki ,  Katsunobu Mori

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L24/10 ,  H01L23/3114 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05546 ,  H01L2224/05567 ,  H01L2224/13 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13099 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2224/05552 ,  H01L2924/00

摘要： A manufacturing method of a semiconductor device, comprising the steps of forming an insulation layer, which has an opening section in an area including an area on an electrode pad, on a top surface of the semiconductor substrate on which the electrode pad is formed; at least forming a first barrier metal layer, which becomes a part of a leading wiring layer, in an inner peripheral surface of the opening section including the top surface of the electrode pad; at least forming a main conductor layer, which becomes a part of the leading wiring layer, in an area surrounded by the first barrier metal layer in the opening section; eliminating an upper portion of the main conductor layer at least to a position at which the first barrier metal layer is exposed, and forming a second barrier metal layer, which becomes a part of the leading wiring layer, so as to cover the whole top surface of the main conductor layer.

摘要翻译： 一种半导体器件的制造方法，包括以下步骤：在形成有电极焊盘的半导体衬底的顶表面上形成绝缘层，该绝缘层在包括电极焊盘的区域的区域中具有开口部分; 至少在包括所述电极焊盘的顶面的所述开口部的内周面中形成成为前导布线层的一部分的第一阻挡金属层; 至少在由开口部分中的第一阻挡金属层包围的区域中形成成为引导布线层的一部分的主导体层; 消除主导体层的上部至少到第一阻挡金属层露出的位置，形成作为引导布线层的一部分的第二阻挡金属层，以覆盖整个顶表面 的主导体层。

公开(公告)号：US20050104165A1

公开(公告)日：2005-05-19

申请号：US11023389

申请日：2004-12-29

申请人： Toshiya Ishio ,  Hiroyuki Nakanishi ,  Katsunobu Mori ,  Yoshihide Iwazaki ,  Shinji Suminoe

发明人： Toshiya Ishio ,  Hiroyuki Nakanishi ,  Katsunobu Mori ,  Yoshihide Iwazaki ,  Shinji Suminoe

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/552 ,  H01L29/06 ,  H01L21/302

CPC分类号： H01L23/552 ,  H01L23/3114 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L29/0657 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10158 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor chip of the present invention is so arranged that a front face on which an element circuit is formed has electrode pads and a side face and a back face are coated with a shielding layer for shielding electromagnetic waves. With this, it is possible to provide a semiconductor element capable of being easily manufactured into a smaller semiconductor device compared with a conventional semiconductor device equipped with a shielding cap; a semiconductor device; and a method for manufacturing a semiconductor element.

摘要翻译： 本发明的半导体芯片被布置成使得其上形成有元件电路的正面具有电极焊盘，并且侧面和背面涂覆有用于屏蔽电磁波的屏蔽层。 由此，与配备有屏蔽盖的现有的半导体装置相比，可以提供能够容易地制造成较小的半导体装置的半导体元件; 半导体器件; 以及半导体元件的制造方法。

公开(公告)号：US07445958B2

公开(公告)日：2008-11-04

申请号：US11474469

申请日：2006-06-26

申请人： Shinji Suminoe ,  Hiroyuki Nakanishi ,  Toshiya Ishio ,  Yoshihide Iwazaki ,  Katsunobu Mori

发明人： Shinji Suminoe ,  Hiroyuki Nakanishi ,  Toshiya Ishio ,  Yoshihide Iwazaki ,  Katsunobu Mori

IPC分类号： H01L21/44

CPC分类号： H01L24/10 ,  H01L23/3114 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05546 ,  H01L2224/05567 ,  H01L2224/13 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13099 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2224/05552 ,  H01L2924/00

摘要： A manufacturing method of a semiconductor device, comprising the steps of forming an insulation layer, which has an opening section in an area including an area on an electrode pad, on a top surface of the semiconductor substrate on which the electrode pad is formed; at least forming a first barrier metal layer, which becomes a part of a leading wiring layer, in an inner peripheral surface of the opening section including the top surface of the electrode pad; at least forming a main conductor layer, which becomes a part of the leading wiring layer, in an area surrounded by the first barrier metal layer in the opening section; eliminating an upper portion of the main conductor layer at least to a position at which the first barrier metal layer is exposed, and forming a second barrier metal layer, which becomes a part of the leading wiring layer, so as to cover the whole top surface of the main conductor layer.

摘要翻译： 一种半导体器件的制造方法，包括以下步骤：在形成有电极焊盘的半导体衬底的顶表面上形成绝缘层，该绝缘层在包括电极焊盘的区域的区域中具有开口部分; 至少在包括所述电极焊盘的顶面的所述开口部的内周面中形成成为前导布线层的一部分的第一阻挡金属层; 至少在由开口部分中的第一阻挡金属层包围的区域中形成成为引导布线层的一部分的主导体层; 消除主导体层的上部至少到第一阻挡金属层露出的位置，形成作为引导布线层的一部分的第二阻挡金属层，以覆盖整个顶表面 的主导体层。

公开(公告)号：US07091616B2

公开(公告)日：2006-08-15

申请号：US10163492

申请日：2002-06-07

申请人： Shinji Suminoe ,  Hiroyuki Nakanishi ,  Toshiya Ishio ,  Yoshihide Iwazaki ,  Katsunobu Mori

发明人： Shinji Suminoe ,  Hiroyuki Nakanishi ,  Toshiya Ishio ,  Yoshihide Iwazaki ,  Katsunobu Mori

IPC分类号： H01L23/48

CPC分类号： H01L24/10 ,  H01L23/3114 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05546 ,  H01L2224/05567 ,  H01L2224/13 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13099 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2224/05552 ,  H01L2924/00

摘要： A leading wiring layer is provided with a main conductor layer, a first barrier metal layer for covering bottom and side surfaces of the main conductor layer, and a second barrier metal layer for covering a top surface of the main conductor layer. This ensures the respective barrier metal layers to cover entire surroundings including the side, bottom and top surfaces of the main conductor layer.

摘要翻译： 引导布线层设置有主导体层，用于覆盖主导体层的底部和侧表面的第一阻挡金属层和用于覆盖主导体层的顶表面的第二阻挡金属层。 这确保相应的阻挡金属层覆盖包括主导体层的侧面，底部和顶部表面的整个环境。

公开(公告)号：US06831002B2

公开(公告)日：2004-12-14

申请号：US10242422

申请日：2002-09-13

申请人： Yoshihide Iwazaki ,  Shinji Suminoe ,  Hiroyuki Nakanishi ,  Toshiya Ishio ,  Takamasa Tanaka ,  Katsunobu Mori

发明人： Yoshihide Iwazaki ,  Shinji Suminoe ,  Hiroyuki Nakanishi ,  Toshiya Ishio ,  Takamasa Tanaka ,  Katsunobu Mori

IPC分类号： H01L244763

CPC分类号： H01L21/76882 ,  H01L21/2885 ,  H01L21/76898

摘要： A manufacturing method of a semiconductor device for providing wires on a front surface of a semiconductor wafer by providing a plating layer, in which conductive layers provided on the front and back surfaces of the semiconductor wafer are electrically conducted by solder filled in its through-holes, and electrolytic plating is carried out by electrically connecting cathode terminals of an electrolytic plating apparatus and the conductive layer provided on the back surface of the semiconductor wafer which is provided with a mask on the conductive layer provided on its front surface.

摘要翻译： 一种半导体器件的制造方法，其通过提供镀层，在半导体晶片的前表面上提供导线，其中设置在半导体晶片的前表面和后表面上的导电层通过填充在其通孔中的焊料电导电 并且通过将电解电镀装置的阴极端子与设置在其前表面上的导电层上设置有掩模的半导体晶片的背面上的导电层电连接进行电解电镀。

公开(公告)号：US06396157B2

公开(公告)日：2002-05-28

申请号：US09752682

申请日：2001-01-03

申请人： Hiroyuki Nakanishi ,  Katsunobu Mori ,  Toshiya Ishio ,  Shinji Suminoe

发明人： Hiroyuki Nakanishi ,  Katsunobu Mori ,  Toshiya Ishio ,  Shinji Suminoe

IPC分类号： H01L2348

CPC分类号： H01L24/11 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/0001 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/14

摘要： A semiconductor integrated circuit device in accordance with the present invention is provided with first electrode pads, a first insulation layer and a second insulation layer. The first electrode pad are formed on the circuit formation face side of an IC chip. The first insulation layer is placed on areas other than the upper portions of the first electrode pads. The second insulation layer, which is made from a photosensitive material, is formed on the first insulation layer with an opening section for allowing at least one portion of the first electrode, the wire and at least one portion of the second electrode to be exposed. Here, the wire and the second electrode are formed by filling the opening section of the second insulation layer with particles of a conductive material. Thus, it is possible to provide a semiconductor integrated circuit device to which a fine wire processing technique is applied while maintaining the same functions as conventional devices at low costs, and a manufacturing method for such a device.

摘要翻译： 根据本发明的半导体集成电路器件设置有第一电极焊盘，第一绝缘层和第二绝缘层。 第一电极焊盘形成在IC芯片的电路形成面侧。 第一绝缘层放置在除第一电极焊盘的上部之外的区域上。 由感光材料制成的第二绝缘层在第一绝缘层上形成有用于允许第一电极，电线和至少一部分第二电极的至少一部分露出的开口部分。 这里，通过用导电材料的颗粒填充第二绝缘层的开口部分来形成电线和第二电极。 因此，可以提供一种半导体集成电路器件，在保持与传统器件相同功能的低成本的条件下应用细线加工技术，以及这种器件的制造方法。

公开(公告)号：US06552426B2

公开(公告)日：2003-04-22

申请号：US09847314

申请日：2001-05-03

申请人： Toshiya Ishio ,  Hiroyuki Nakanishi ,  Katsunobu Mori

发明人： Toshiya Ishio ,  Hiroyuki Nakanishi ,  Katsunobu Mori

IPC分类号： H01L2352

CPC分类号： H01L24/97 ,  H01L23/3121 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06558 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present invention provides a quality and reliable high-density package (Chip Size Package) semiconductor device without problems related to the manufacturing process. The semiconductor device includes the first semiconductor substrate piece having electrode pads formed on its principle surface, and a second semiconductor mounting piece mounted thereon via a first insulating film and a die-attaching material. On the surface opposite the first semiconductor substrate piece of the second semiconductor substrate piece, formed are wiring patterns and a second insulating film for protecting the wiring patterns. The wiring patterns include electrode pads, wires, and lands where external connection terminals are provided.

摘要翻译： 本发明提供了质量可靠的高密度封装（芯片尺寸封装）半导体器件，而与制造工艺无关。 半导体器件包括：第一半导体衬底片，其具有形成在其主表面上的电极焊盘;以及第二半导体安装件，其经由第一绝缘膜和管芯附着材料安装在其上。 在与第二半导体衬底片的第一半导体衬底片相对的表面上形成布线图案和用于保护布线图案的第二绝缘膜。 布线图案包括设置有外部连接端子的电极焊盘，电线和焊盘。

公开(公告)号：US06921980B2

公开(公告)日：2005-07-26

申请号：US10059113

申请日：2002-01-31

申请人： Hiroyuki Nakanishi ,  Toshiya Ishio ,  Katsunobu Mori

发明人： Hiroyuki Nakanishi ,  Toshiya Ishio ,  Katsunobu Mori

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065 ,  H01L25/16 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L23/3114 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/16 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05184 ,  H01L2224/05548 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/16265 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19104 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/05647 ,  H01L2224/05166 ,  H01L2924/00012

摘要： An integrated semiconductor circuit includes a semiconductor chip on which surface a plurality of connection electrodes are formed, a lower insulating layer covering the surface of the semiconductor chip such that the connection electrodes are exposed, a plurality of wiring portions formed on the lower insulating layer, each of the wiring portions being connected to the connection electrode at one end and provided with a component connection portion at the other end, an upper insulating layer covering the wiring portions such that the component connection portions are exposed, and an electronic component connected between different component connection portions.

摘要翻译： 集成半导体电路包括其上形成有多个连接电极的表面的半导体芯片，覆盖半导体芯片的表面的下绝缘层，使得连接电极露出，形成在下绝缘层上的多个布线部分， 每个布线部分在一端连接到连接电极，并且在另一端处设置有部件连接部分，覆盖布线部分的上绝缘层使得部件连接部分暴露，以及连接在不同的部件之间的电子部件 部件连接部分。

公开(公告)号：US6104084A

公开(公告)日：2000-08-15

申请号：US61035

申请日：1998-04-16

申请人： Toshiya Ishio ,  Hiroyuki Nakanishi ,  Tomoyo Maruyama ,  Katsunobu Mori ,  Katsuyuki Tarui

发明人： Toshiya Ishio ,  Hiroyuki Nakanishi ,  Tomoyo Maruyama ,  Katsunobu Mori ,  Katsuyuki Tarui

IPC分类号： H01L25/18 ,  H01L23/495 ,  H01L25/065 ,  H01L25/07 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/49 ,  H01L23/49531 ,  H01L23/49575 ,  H01L24/32 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48639 ,  H01L2224/4911 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85439 ,  H01L2224/92247 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/351

摘要： An insulation material and a wire pattern are provided on at least one of the surfaces of a die pad. Wires of the wire pattern are patterned in such a manner that at least one inner lead included in at least one of two lead groups is electrically connected to an electrode pad provided on the element forming surface of the semiconductor chip near the side edge other than the side edge opposing the lead group including the above particular inner lead, while at least one inner lead included in the other lead group is electrically connected to an electrode pad provided on the element forming surface of the semiconductor chip near the side edge other than the side edge opposing the other lead group. Accordingly, a multichip-1-package semiconductor device using any kind of semiconductor chip can be realized. Also, the costs of the semiconductor device are saved and the semiconductor device can be developed in a shorter period by omitting the design modification of the semiconductor chip.

摘要翻译： 在芯片焊盘的至少一个表面上设置绝缘材料和导线图案。 线图案的线图案化为使得包括在两个引线组中的至少一个中的至少一个内引线电连接到设置在半导体芯片的元件形成表面附近的电极焊盘，该电极焊盘靠近除了 与包括上述特定内引线的引线组相对的侧边缘，而另一引线组中包括的至少一个内引线电连接到设置在半导体芯片的元件形成表面上的电极焊盘，靠近侧边 边缘反对另一个领导组。 因此，可以实现使用任何种类的半导体芯片的多芯片1封装半导体器件。 此外，通过省略半导体芯片的设计修改，节省了半导体器件的成本，并且可以在更短的时间内开发半导体器件。