公开(公告)号：US06448661B1

公开(公告)日：2002-09-10

申请号：US10059932

申请日：2002-01-28

申请人： Hyeong-Seob Kim ,  Sa-Yoon Kang ,  Myung-Kee Chung ,  In-Ku Kang ,  Kwan-Jai Lee

发明人： Hyeong-Seob Kim ,  Sa-Yoon Kang ,  Myung-Kee Chung ,  In-Ku Kang ,  Kwan-Jai Lee

IPC分类号： H01L2348

CPC分类号： H01L24/83 ,  H01L23/481 ,  H01L24/29 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/0781 ,  H01L2924/07811 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299

摘要： A three-dimensional, multi-chip package with chip selection pads formed at the chip-level and a manufacturing method thereof are provided. The three-dimensional, multi-chip package is formed by stacking a number (N) of semiconductor integrated circuit chips. Each chip comprises an integrated circuit die, a chip selection terminal, (N−1) chip selection pads, an insulation layer, (N−1) metal wirings, upper connection terminals, lower connection terminals, and trench wirings. The chip selection terminal of each chip is separated from the chip selection of the other chips by the chip selection pads formed at the chip-level.

摘要翻译： 提供了一种具有在芯片级形成的芯片选择焊盘的三维多芯片封装及其制造方法。 通过堆叠多个（N）个半导体集成电路芯片来形成三维多芯片封装。 每个芯片包括集成电路管芯，芯片选择端子（N-1）芯片选择焊盘，绝缘层，（N-1）金属布线，上连接端子，下连接端子和沟槽布线。 每个芯片的芯片选择端通过在芯片级形成的芯片选择焊盘与其他芯片的芯片选择分离。

公开(公告)号：US20050023683A1

公开(公告)日：2005-02-03

申请号：US10877733

申请日：2004-06-25

申请人： Myung-Kee Chung ,  Min-Keun Kwak ,  Kil-Soo Kim

发明人： Myung-Kee Chung ,  Min-Keun Kwak ,  Kil-Soo Kim

IPC分类号： H01L23/12 ,  H01L23/498 ,  H01L23/50 ,  H05K1/11 ,  H05K3/34 ,  H01L23/48 ,  H01L23/52

CPC分类号： H05K1/111 ,  H01L23/49816 ,  H01L2224/81385 ,  H01L2924/0002 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/09663 ,  H05K2201/09809 ,  H05K2201/0989 ,  H05K2201/099 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00

摘要： A semiconductor package has ball lands each configured to have a composite structure of SMD type and NSMD type. One peripheral portion of the ball land is covered with a mask layer, thus forming the SMD type, whereas the other peripheral portion is exposed through an opening area of the mask layer, thus forming the NSMD type. In one embodiment, the first peripheral portion is disposed to face a central point of a ball-mounting surface of a substrate, and the second peripheral portion is disposed to face the opposite direction to the central point. The composite structure of the ball lands provides more stable and enhanced connections between connection balls, such as solder balls, and the ball-mounting surface.

摘要翻译： 半导体封装具有各自被配置为具有SMD型和NSMD型的复合结构的球形焊盘。 球面的一个周边部分被掩模层覆盖，从而形成SMD型，而另一个周边部分通过掩模层的开口区域露出，从而形成NSMD型。 在一个实施例中，第一周边部分设置成面对基板的球安装表面的中心点，并且第二周边部分设置成面向与中心点相反的方向。 球面的复合结构在连接球（例如焊球）和球安装表面之间提供更稳定和增强的连接。

公开(公告)号：US07807507B2

公开(公告)日：2010-10-05

申请号：US12476601

申请日：2009-06-02

申请人： Won-Keun Kim ,  Myung-Kee Chung ,  Myung-Sung Kang

发明人： Won-Keun Kim ,  Myung-Kee Chung ,  Myung-Sung Kang

IPC分类号： H01L21/78

CPC分类号： H01L21/563 ,  H01L21/6836 ,  H01L25/0657 ,  H01L2221/68381 ,  H01L2224/73203 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/01078

摘要： A semiconductor package forming method includes mounting a backgrinding-underfill film which includes a laminated backgrinding film and a laminated underfill film on a semiconductor wafer so that the underfill film adheres to a front side of the semiconductor wafer; backgrinding a back side of the semiconductor wafer on which the backgrinding-underfill film has been mounted and removing the backgrinding film of the backgrinding-underfill film from the semiconductor wafer. The method further includes dicing the semiconductor wafer from which the backgrinding film has been removed, so that semiconductor chips are separated from the semiconductor wafer.

摘要翻译： 半导体封装形成方法包括在半导体晶片上安装包括层压背面研磨膜和层叠底部填充膜的背面研磨底部填充膜，使得底部填充膜粘附到半导体晶片的正面; 背面研磨已经安装了背面研磨底部填充膜的半导体晶片的背面，并从半导体晶片去除背面研磨底部填充膜的背面研磨膜。 该方法还包括对已经去除背面研磨膜的半导体晶片进行切割，使得半导体芯片与半导体晶片分离。

公开(公告)号：US07064435B2

公开(公告)日：2006-06-20

申请号：US10877733

申请日：2004-06-25

申请人： Myung-Kee Chung ,  Min-Keun Kwak ,  Kil-Soo Kim

发明人： Myung-Kee Chung ,  Min-Keun Kwak ,  Kil-Soo Kim

IPC分类号： H01L23/48

CPC分类号： H05K1/111 ,  H01L23/49816 ,  H01L2224/81385 ,  H01L2924/0002 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/09663 ,  H05K2201/09809 ,  H05K2201/0989 ,  H05K2201/099 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00

摘要： A semiconductor package has ball lands each configured to have a composite structure of SMD type and NSMD type. One peripheral portion of the ball land is covered with a mask layer, thus forming the SMD type, whereas the other peripheral portion is exposed through an opening area of the mask layer, thus forming the NSMD type. In one embodiment, the first peripheral portion is disposed to face a central point of a ball-mounting surface of a substrate, and the second peripheral portion is disposed to face the opposite direction to the central point. The composite structure of the ball lands provides more stable and enhanced connections between connection balls, such as solder balls, and the ball-mounting surface.

摘要翻译： 半导体封装具有各自被配置为具有SMD型和NSMD型的复合结构的球形焊盘。 球面的一个周边部分被掩模层覆盖，从而形成SMD型，而另一个周边部分通过掩模层的开口区域露出，从而形成NSMD型。 在一个实施例中，第一周边部分设置成面对基板的球安装表面的中心点，并且第二周边部分设置成面向与中心点相反的方向。 球面的复合结构在连接球（例如焊球）和球安装表面之间提供更稳定和增强的连接。

公开(公告)号：US20100285635A1

公开(公告)日：2010-11-11

申请号：US12840656

申请日：2010-07-21

申请人： Cha-Jea Jo ,  Myung-Kee Chung ,  Nam-Seog Kim ,  In-Young Lee ,  Seok-Ho Kim ,  Ho-Jin Lee ,  Ju-Il Choi ,  Chang-Woo Shin

发明人： Cha-Jea Jo ,  Myung-Kee Chung ,  Nam-Seog Kim ,  In-Young Lee ,  Seok-Ho Kim ,  Ho-Jin Lee ,  Ju-Il Choi ,  Chang-Woo Shin

IPC分类号： H01L21/60 ,  H01L21/50

CPC分类号： H01L23/3128 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/15311 ,  H01L2224/05599

摘要： A chip stack package includes a substrate, a plurality of chips, a plurality of adhesive layers and a plug. The substrate has a wiring pattern and a seed layer formed on the wiring pattern. Each of the chips has an electrode pad and a first through-hole that penetrates the electrode pad. The chips are stacked such that the first through-holes are aligned on the seed layer of the substrate. The adhesive layers are interposed between the substrate and one of the chips, as well as between the chips. Each of the adhesive layers has a second through-hole connected to the first through-hole. The plug fills up the first through-holes and the second through-holes and electrically connects the electrode pads to the wiring pattern of the substrate. A cross-sectional area of the plug in the second through-holes may be larger than that of the plug in the first through-holes.

摘要翻译： 芯片堆叠封装包括基板，多个芯片，多个粘合剂层和插头。 基板具有形成在布线图案上的布线图案和种子层。 每个芯片具有电极焊盘和穿过电极焊盘的第一通孔。 芯片被堆叠，使得第一通孔在衬底的籽晶层上排列。 粘合层介于基片和芯片之一之间以及芯片之间。 每个粘合层具有连接到第一通孔的第二通孔。 插头填充第一通孔和第二通孔，并将电极焊盘电连接到衬底的布线图案。 第二通孔中的插塞的横截面面积可以大于第一通孔中的插头的横截面面积。

公开(公告)号：US08088648B2

公开(公告)日：2012-01-03

申请号：US12840656

申请日：2010-07-21

申请人： Cha-Jea Jo ,  Myung-Kee Chung ,  Nam-Seog Kim ,  In-Young Lee ,  Seok-Ho Kim ,  Ho-Jin Lee ,  Ju-Il Choi ,  Chang-Woo Shin

发明人： Cha-Jea Jo ,  Myung-Kee Chung ,  Nam-Seog Kim ,  In-Young Lee ,  Seok-Ho Kim ,  Ho-Jin Lee ,  Ju-Il Choi ,  Chang-Woo Shin

IPC分类号： H01L21/50 ,  H01L21/60

CPC分类号： H01L23/3128 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/15311 ,  H01L2224/05599

摘要： A chip stack package includes a substrate, a plurality of chips, a plurality of adhesive layers and a plug. The substrate has a wiring pattern and a seed layer formed on the wiring pattern. Each of the chips has an electrode pad and a first through-hole that penetrates the electrode pad. The chips are stacked such that the first through-holes are aligned on the seed layer of the substrate. The adhesive layers are interposed between the substrate and one of the chips, as well as between the chips. Each of the adhesive layers has a second through-hole connected to the first through-hole. The plug fills up the first through-holes and the second through-holes and electrically connects the electrode pads to the wiring pattern of the substrate. A cross-sectional area of the plug in the second through-holes may be larger than that of the plug in the first through-holes.

摘要翻译： 芯片堆叠封装包括基板，多个芯片，多个粘合剂层和插头。 基板具有形成在布线图案上的布线图案和种子层。 每个芯片具有电极焊盘和穿过电极焊盘的第一通孔。 芯片被堆叠，使得第一通孔在衬底的籽晶层上排列。 粘合层介于基片和芯片之一之间以及芯片之间。 每个粘合层具有连接到第一通孔的第二通孔。 插头填充第一通孔和第二通孔，并将电极焊盘电连接到衬底的布线图案。 第二通孔中的插塞的横截面面积可以大于第一通孔中的插头的横截面面积。

公开(公告)号：US07588964B2

公开(公告)日：2009-09-15

申请号：US11790173

申请日：2007-04-24

申请人： Yong-Chai Kwon ,  Dong-Ho Lee ,  Myung-Kee Chung ,  Kang-Wook Lee ,  Sun-Won Kang ,  Keum-Hee Ma

发明人： Yong-Chai Kwon ,  Dong-Ho Lee ,  Myung-Kee Chung ,  Kang-Wook Lee ,  Sun-Won Kang ,  Keum-Hee Ma

IPC分类号： H01L23/02

CPC分类号： H01L25/0657 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/12 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/90 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13009 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/83856 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

摘要： A stacked structure of semiconductor devices may include a plurality of stacked semiconductor devices, each having an upper surface and a lower surface and one or more via electrodes protruding from the upper surface to the lower surface. The via-electrodes may have upper parts (heads) protruding from the upper surface and lower parts (ends) protruding from the lower surface. The stacked semiconductor devices may be electrically connected to each other through the via-electrodes. A first adhesive film (e.g., patternable material) and a second adhesive film (e.g. puncturable material) may be formed between the stacked semiconductor devices. The stacked structure of semiconductor devices may be mounted on the upper surface of a printed circuit board (PCB) having a mount-specific adhesive film to form a semiconductor device package. The mounted stacked structure and the upper surface of the PCB may be further covered with a molding material.

摘要翻译： 半导体器件的层叠结构可以包括多个层叠的半导体器件，每个具有上表面和下表面以及从上表面到下表面突出的一个或多个通孔电极。 通孔电极可以具有从上表面突出的上部（头）和从下表面突出的下部（端部）。 层叠的半导体器件可以通过通孔电极彼此电连接。 可以在层叠的半导体器件之间形成第一粘合膜（例如，可图案化材料）和第二粘合膜（例如可刺穿材料）。 半导体器件的堆叠结构可以安装在具有安装专用粘合剂膜的印刷电路板（PCB）的上表面上以形成半导体器件封装。 安装的堆叠结构和PCB的上表面可以进一步被模制材料覆盖。

公开(公告)号：US20080169545A1

公开(公告)日：2008-07-17

申请号：US11790173

申请日：2007-04-24

申请人： Yong-Chai Kwon ,  Dong-Ho Lee ,  Myung-Kee Chung ,  Kang-Wook Lee ,  Sun-Won Kang ,  Keum-Hee Ma

发明人： Yong-Chai Kwon ,  Dong-Ho Lee ,  Myung-Kee Chung ,  Kang-Wook Lee ,  Sun-Won Kang ,  Keum-Hee Ma

IPC分类号： H01L23/02 ,  H01L21/00

CPC分类号： H01L25/0657 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/12 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/90 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13009 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/83856 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

摘要： A stacked structure of semiconductor devices may include a plurality of stacked semiconductor devices, each having an upper surface and a lower surface and one or more via electrodes protruding from the upper surface to the lower surface. The via-electrodes may have upper parts (heads) protruding from the upper surface and lower parts (ends) protruding from the lower surface. The stacked semiconductor devices may be electrically connected to each other through the via-electrodes. A first adhesive film (e.g., patternable material) and a second adhesive film (e.g. puncturable material) may be formed between the stacked semiconductor devices. The stacked structure of semiconductor devices may be mounted on the upper surface of a printed circuit board (PCB) having a mount-specific adhesive film to form a semiconductor device package. The mounted stacked structure and the upper surface of the PCB may be further covered with a molding material.

摘要翻译： 半导体器件的层叠结构可以包括多个层叠的半导体器件，每个具有上表面和下表面以及从上表面到下表面突出的一个或多个通孔电极。 通孔电极可以具有从上表面突出的上部（头）和从下表面突出的下部（端部）。 层叠的半导体器件可以通过通孔电极彼此电连接。 可以在层叠的半导体器件之间形成第一粘合膜（例如，可图案化材料）和第二粘合膜（例如可刺穿材料）。 半导体器件的堆叠结构可以安装在具有安装专用粘合剂膜的印刷电路板（PCB）的上表面上以形成半导体器件封装。 安装的堆叠结构和PCB的上表面可以进一步被模制材料覆盖。