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公开(公告)号：US10342160B2
公开(公告)日：2019-07-02
申请号：US15802560
申请日：2017-11-03
IPC分类号： H05K7/20 , H01L23/367 , H01L23/40
摘要： Structures and methods for providing heat sink attachments on existing heat sinks. According to a device, a first heat sink comprises a first base and fins extending from the first base. The first base comprises a cutout therein and a first base bottom surface contacting a first electronic component. A second heat sink comprises a second base and fins extending from the second base. The second heat sink is located in the cutout of the first heat sink. The second base comprises a second base bottom surface contacting a second electronic component. A pressure plate is attached to the first heat sink and overlays the second heat sink. The pressure plate contacts the second heat sink and applies pressure between the second heat sink and the second electronic component.
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公开(公告)号：US20180213645A1
公开(公告)日：2018-07-26
申请号：US15928874
申请日：2018-03-22
发明人： Michael A. Gaynes , Jeffrey D. Gelorme , Robert P. Kuder, II , Daniel J. Littrell , Thomas E. Lombardi , Marie-Claude Paquet , Frank L. Pompeo , David L. Questad , James Speidell , Sri M. Sri-Jayantha , Son K. Tran
CPC分类号： H05K1/18 , H01R4/02 , H01R12/51 , H01R12/7041 , H01R43/205 , H05K1/0271 , H05K1/181 , H05K3/30 , H05K3/305 , H05K3/366 , H05K2201/10015 , H05K2201/10022 , H05K2201/1003 , H05K2201/10106 , H05K2201/10159 , H05K2201/10166 , H05K2201/10977
摘要： An interconnect structure that includes a component circuit board containing a plurality of electrical components, and a wafer connector assembly. The wafer connector assembly includes a plurality of interconnect circuit boards that are in electrical connection with the components circuit board through a plurality of rows of solder joints, the plurality of interconnect circuit boards having a connection end including at least one contact. An adhesive is present structurally reinforcing at least a row of the solder joints that is proximate to the connection end of the plurality of interconnect circuit boards of the wafer assembly.
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3.发明申请公开(公告)号：US20180082912A1
公开(公告)日：2018-03-22
申请号：US15826975
申请日：2017-11-30
发明人： William E. Bernier , Timothy H. Daubenspeck , Virendra R. Jadhav , Valerie A. Oberson , David L. Questad
CPC分类号： H01L22/30 , B05D1/36 , G01N3/60 , G01N19/04 , G01N25/16 , G01N2203/0296 , G01N2203/0298 , H01L24/13 , H01L2224/131 , H01L2924/10253 , H01L2924/351 , H01L2924/014 , H01L2924/00
摘要： A symmetrical, flat laminate structure used to minimize variables in a test structure to experimentally gauge white bump sensitivity to CTE mismatch is disclosed. The test structure includes a flat laminate structure. The method of using the test structure includes isolating a cause of a multivariable chip join problem that is adversely impacted by warpage and quantifying a contribution of the warpage, itself, in a formation of the multivariable chip join problem.
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公开(公告)号：US20180076101A1
公开(公告)日：2018-03-15
申请号：US15813536
申请日：2017-11-15
发明人： Sushumna Iruvanti , Shidong Li , Marek A. Orlowski , David L. Questad , Tuhin Sinha , Krishna R. Tunga , Thomas A. Wassick , Randall J. Werner , Jeffrey A. Zitz
IPC分类号： H01L21/66 , H01L21/48 , H01L23/498 , G06F17/50
CPC分类号： H01L22/32 , G06F17/5068 , H01L21/4857 , H01L21/486 , H01L23/49822 , H01L23/49827 , H01L23/49866 , H01L2224/16225 , H01L2924/15311
摘要： A laminate includes a plurality of buildup layers disposed on a core and a plurality of unit cells defined in the buildup layers. Each unit cell includes: at least one test via that passes through at least two of the buildup layers and that is electrically connected to testing locations on a probe accessible location of the laminate; and two or more dummy vias disposed in the unit cell. The dummy vias are arranged in the unit cell at one of a plurality of distances from the test via.
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5.发明授权Overcoming chip warping to enhance wetting of solder bumps and flip chip attaches in a flip chip package 有权克服芯片翘曲以增强焊料凸块的润湿和倒装芯片连接在倒装芯片封装中公开(公告)号：US08927334B2
公开(公告)日：2015-01-06
申请号：US13626032
申请日：2012-09-25
发明人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Nathalie Normand , David L. Questad , Wolfgang Sauter , Timothy D. Sullivan
CPC分类号： H01L23/3164 , H01L23/291 , H01L23/293 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/11001 , H01L2224/11011 , H01L2224/1131 , H01L2224/11849 , H01L2224/13111 , H01L2224/16225 , H01L2224/16227 , H01L2224/81007 , H01L2224/81191 , H01L2924/12042 , H01L2924/15174 , H01L2924/15311 , H01L2924/3511 , H01L2924/00014 , H01L2924/00012 , H01L2924/01047 , H01L2924/00
摘要： Structures and methods for forming good electrical connections between an integrated circuit (IC) chip and a chip carrier of a flip chip package include forming one of: a tensile layer on a front side of the IC chip, which faces a tops surface of the chip carrier, and a compressive layer on the backside of the IC chip. Addition of one of: a tensile layer to the front side of the IC chip and a compressive layer the backside of the IC chip, may reduce or modulate warpage of the IC chip and enhance wetting of opposing solder surfaces of solder bumps on the IC chip and solder formed on flip chip (FC) attaches of a chip carrier during making of the flip chip package.
摘要翻译： 用于在集成电路（IC）芯片和倒装芯片封装的芯片载体之间形成良好电连接的结构和方法包括形成以下之一：IC芯片正面上的面向芯片顶表面的拉伸层 载体和IC芯片背面的压缩层。 添加IC芯片的前侧的拉伸层和IC芯片的背面的压缩层可以减少或调制IC芯片的翘曲并增强IC芯片上的焊料凸块的相对焊接表面的润湿 并且在制造倒装芯片封装期间在芯片载体的倒装芯片（FC）上形成焊料。
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公开(公告)号：US10381276B2
公开(公告)日：2019-08-13
申请号：US14973165
申请日：2015-12-17
发明人： Sushumna Iruvanti , Shidong Li , Marek A. Orlowski , David L. Questad , Tuhin Sinha , Krishna R. Tunga , Thomas A. Wassick , Randall J. Werner , Jeffrey A. Zitz
IPC分类号： H01L21/48 , G06F17/50 , H01L21/66 , H01L23/498
摘要： A laminate includes a plurality of buildup layers disposed on a core and a plurality of unit cells defined in the buildup layers. Each unit cell includes: at least one test via that passes through at least two of the buildup layers and that is electrically connected to testing locations on a probe accessible location of the laminate; and two or more dummy vias disposed in the unit cell. The dummy vias are arranged in the unit cell at one of a plurality of distances from the test via.
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公开(公告)号：US10368441B2
公开(公告)日：2019-07-30
申请号：US15928874
申请日：2018-03-22
发明人： Michael A. Gaynes , Jeffrey D. Gelorme , Robert P. Kuder, II , Daniel J. Littrell , Thomas E. Lombardi , Marie-Claude Paquet , Frank L. Pompeo , David L. Questad , James Speidell , Sri M. Sri-Jayantha , Son K. Tran
IPC分类号： H01R13/405 , H01R43/24 , H05K1/18 , H01R12/51 , H01R43/20 , H05K3/30 , H01R12/70 , H05K3/36 , H01R4/02 , H05K1/02
摘要： An interconnect structure that includes a component circuit board containing a plurality of electrical components, and a wafer connector assembly. The wafer connector assembly includes a plurality of interconnect circuit boards that are in electrical connection with the components circuit board through a plurality of rows of solder joints, the plurality of interconnect circuit boards having a connection end including at least one contact. An adhesive is present structurally reinforcing at least a row of the solder joints that is proximate to the connection end of the plurality of interconnect circuit boards of the wafer assembly.
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公开(公告)号：US10249548B2
公开(公告)日：2019-04-02
申请号：US15813536
申请日：2017-11-15
发明人： Sushumna Iruvanti , Shidong Li , Marek A. Orlowski , David L. Questad , Tuhin Sinha , Krishna R. Tunga , Thomas A. Wassick , Randall J. Werner , Jeffrey A. Zitz
IPC分类号： H01L21/00 , H01L21/66 , G06F17/50 , H01L23/498 , H01L21/48
摘要： A laminate includes a plurality of buildup layers disposed on a core and a plurality of unit cells defined in the buildup layers. Each unit cell includes: at least one test via that passes through at least two of the buildup layers and that is electrically connected to testing locations on a probe accessible location of the laminate; and two or more dummy vias disposed in the unit cell. The dummy vias are arranged in the unit cell at one of a plurality of distances from the test via.
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公开(公告)号：US20180054915A1
公开(公告)日：2018-02-22
申请号：US15802560
申请日：2017-11-03
IPC分类号： H05K7/20 , H01L23/367 , H01L23/40
CPC分类号： H05K7/2039 , H01L23/367 , H01L23/4006 , H05K7/20409
摘要： Structures and methods for providing heat sink attachments on existing heat sinks. According to a device, a first heat sink comprises a first base and fins extending from the first base. The first base comprises a cutout therein and a first base bottom surface contacting a first electronic component. A second heat sink comprises a second base and fins extending from the second base. The second heat sink is located in the cutout of the first heat sink. The second base comprises a second base bottom surface contacting a second electronic component. A pressure plate is attached to the first heat sink and overlays the second heat sink. The pressure plate contacts the second heat sink and applies pressure between the second heat sink and the second electronic component.
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公开(公告)号：US09627784B1
公开(公告)日：2017-04-18
申请号：US14955466
申请日：2015-12-01
发明人： Michael A. Gaynes , Jeffrey D. Gelorme , Robert P. Kuder, II , Daniel J. Littrell , Thomas E. Lombardi , Marie-Claude Paquet , Frank L. Pompeo , David L. Questad , James Speidell , Sri M. Sri-Jayantha , Son K. Tran
CPC分类号： H05K1/18 , H01L23/12 , H01R4/02 , H01R12/51 , H01R12/7041 , H01R43/205 , H05K1/0271 , H05K1/181 , H05K3/30 , H05K3/305 , H05K3/366 , H05K2201/10015 , H05K2201/10022 , H05K2201/1003 , H05K2201/10106 , H05K2201/10159 , H05K2201/10166 , H05K2201/10977
摘要： An interconnect structure that includes a component circuit board containing a plurality of electrical components, and a wafer connector assembly. The wafer connector assembly includes a plurality of interconnect circuit boards that are in electrical connection with the components circuit board through a plurality of rows of solder joints, the plurality of interconnect circuit boards having a connection end including at least one contact. An adhesive is present structurally reinforcing at least a row of the solder joints that is proximate to the connection end of the plurality of interconnect circuit boards of the wafer assembly.
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