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    Stress-generating shallow trench isolation structure having dual composition
    1.
    发明授权
    Stress-generating shallow trench isolation structure having dual composition 有权
    应力产生浅沟槽隔离结构具有双重组成

    公开(公告)号：US09013001B2

    公开(公告)日：2015-04-21

    申请号：US13947677

    申请日：2013-07-22

    申请人： International Business Machines Corporation

    发明人： Huilong Zhu ,  Jing Wang

    IPC分类号： H01L21/62 ,  H01L23/58 ,  H01L27/088 ,  H01L29/78 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092

    CPC分类号： H01L29/7846 ,  H01L21/3081 ,  H01L21/31053 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/092 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A shallow trench isolation structure containing a first shallow trench isolation portion comprising the first shallow trench material and a second shallow trench isolation portion comprising the second shallow trench material is provided. A first biaxial stress on at least one first active area and a second bidirectional stress on at least one second active area are manipulated separately to enhance charge carrier mobility in middle portions of the at least one first and second active areas by selection of the first and second shallow trench materials as well as adjusting the type of the shallow trench isolation material that each portion of the at least one first active area and the at least one second active area laterally abut.

    摘要翻译： 提供了一种浅沟槽隔离结构，其包含第一浅沟槽隔离部分，其包括第一浅沟槽材料和包括第二浅沟槽材料的第二浅沟槽隔离部分。 在至少一个第二有效区域上的至少一个第一有效区域和第二双向应力上的第一双轴应力被分别操纵以通过选择第一和第二有源区域来增强至少一个第一和第二有源区域的中间部分中的载流子迁移率， 第二浅沟槽材料以及调节所述至少一个第一有源区域和所述至少一个第二有源区域的每个部分横向邻接的浅沟槽隔离材料的类型。

    CMOS structures and methods for improving yield
    4.
    发明授权
    CMOS structures and methods for improving yield 有权
    CMOS结构和提高产量的方法

    公开(公告)号：US09318344B2

    公开(公告)日：2016-04-19

    申请号：US14556732

    申请日：2014-12-01

    申请人： International Business Machines Corporation

    发明人： Huilong Zhu ,  Daewon Yang

    IPC分类号： H01L29/78 ,  H01L21/311 ,  H01L21/8238

    CPC分类号： H01L21/31116 ,  H01L21/823807 ,  H01L21/823864 ,  H01L21/823871 ,  H01L29/7843

    摘要： A simple, effective and economical method to improved the yield of CMOS devices using contact etching stopper liner, including, single neutral stressed liner, single stressed liner and dual stress liner (DSL), technology is provided. In order to improve the chip yield, the present invention provides a method in which a sputter etching process is employed to smooth/flatten (i.e., thin) the top surface of the contact etch stopper liners. When DSL technology is used, the inventive sputter etching process is used to reduce the complexity caused by DSL boundaries to smooth/flatten top surface of the DSL, which results in significant yield increase. The present invention also provides a semiconductor structure including at least one etched liner.

    摘要翻译： 提供了使用接触蚀刻阻挡衬垫（包括单中性应力衬垫，单应力衬垫和双应力衬垫（DSL））技术来提高CMOS器件产量的简单，有效和经济的方法。 为了提高芯片产量，本发明提供了一种使用溅射蚀刻工艺来平滑/平坦化（即，薄）接触蚀刻止动衬片的顶表面的方法。 当使用DSL技术时，本发明的溅射蚀刻工艺用于降低由DSL边界引起的DSL平滑/平坦化表面的复杂性，这导致显着的产量增加。 本发明还提供了包括至少一个蚀刻衬里的半导体结构。

    STRESS-GENERATING STRUCTURE FOR SEMICONDUCTOR-ON-INSULATOR DEVICES
    9.
    发明申请
    STRESS-GENERATING STRUCTURE FOR SEMICONDUCTOR-ON-INSULATOR DEVICES 有权

    公开(公告)号：US20130168804A1

    公开(公告)日：2013-07-04

    申请号：US13778419

    申请日：2013-02-27

    申请人： International Business Machines Corporation

    发明人： Huilong Zhu ,  Brian J. Greene ,  Dureseti Chidambarrao ,  Gregory G. Freeman

    IPC分类号： H01L29/06 ,  H01L21/762

    CPC分类号： H01L29/0603 ,  H01L21/76224 ,  H01L29/1025 ,  H01L29/1054 ,  H01L29/84

    摘要： A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI substrate and enclosing at least one top semiconductor region is formed by lithographic methods and etching. A stress-generating insulator material is deposited in the deep trench and recessed below a top surface of the SOI substrate to form a stress-generating buried insulator plug in the deep trench. A silicon oxide material is deposited in the deep trench, planarized, and recessed. The stack of pad layer is removed to expose substantially coplanar top surfaces of the top semiconductor layer and of silicon oxide plugs. The stress-generating buried insulator plug encloses, and generates a stress to, the at least one top semiconductor region.

    Bonded structure employing metal semiconductor alloy bonding
    10.
    发明授权
    Bonded structure employing metal semiconductor alloy bonding 有权
    使用金属半导体合金结合的结合结构

    公开(公告)号：US09214388B2

    公开(公告)日：2015-12-15

    申请号：US13780810

    申请日：2013-02-28

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Mukta G. Farooq ,  Zhengwen Li ,  Zhijiong Luo ,  Huilong Zhu

    IPC分类号： H01L21/00 ,  H01L21/768 ,  H01L21/20 ,  H01L27/06

    CPC分类号： H01L21/76841 ,  H01L21/2007 ,  H01L27/0688 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896

    摘要： Vertical stacks of a metal portion and a semiconductor portion formed on a first substrate are brought into physical contact with vertical stacks of a metal portion and a semiconductor portion formed on a second substrate. Alternately, vertical stacks of a metal portion and a semiconductor portion formed on a first substrate are brought into physical contact with metal portions formed on a second substrate. The assembly of the first and second substrates is subjected to an anneal at a temperature that induces formation of a metal semiconductor alloy derived from the semiconductor portions and the metal portions. The first substrate and the second substrate are bonded through metal semiconductor alloy portions that adhere to the first and second substrates.

    摘要翻译： 形成在第一基板上的金属部分和半导体部分的垂直叠层与形成在第二基板上的金属部分和半导体部分的垂直叠层物理接触。 或者，形成在第一基板上的金属部分和半导体部分的垂直堆叠与形成在第二基板上的金属部分物理接触。 在引起由半导体部分和金属部分衍生的金属半导体合金的形成的温度下对第一和第二基板的组装进行退火。 第一基板和第二基板通过粘附到第一和第二基板的金属半导体合金部分接合。