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公开(公告)号：US20120068226A1
公开(公告)日：2012-03-22
申请号：US13243521
申请日：2011-09-23
申请人： Jennifer Hydrick , Jizhong Li , Zhiyuan Cheng , James G. Fiorenza , Jie Bai , Ji-Soo Park , Anthony Lochtefeld
发明人： Jennifer Hydrick , Jizhong Li , Zhiyuan Cheng , James G. Fiorenza , Jie Bai , Ji-Soo Park , Anthony Lochtefeld
CPC分类号： H01L21/02538 , H01L21/02381 , H01L21/0245 , H01L21/02461 , H01L21/02463 , H01L21/02543 , H01L21/02546 , H01L21/02636 , H01L21/02639 , H01L21/02647 , H01L29/205 , H01L31/0687 , H01L31/06875 , H01L31/1808 , H01L31/1852 , H01L31/1892 , Y02E10/544
摘要： Methods and structures are provided for formation of devices on substrates including, e.g., lattice-mismatched materials, by the use of aspect ratio trapping and epitaxial layer overgrowth. A method includes forming an opening in a masking layer disposed over a substrate that includes a first semiconductor material. A first layer, which includes a second semiconductor material lattice-mismatched to the first semiconductor material, is formed within the opening. The first layer has a thickness sufficient to extend above a top surface of the masking layer. A second layer, which includes the second semiconductor material, is formed on the first layer and over at least a portion of the masking layer. A vertical growth rate of the first layer is greater than a lateral growth rate of the first layer and a lateral growth rate of the second layer is greater than a vertical growth rate of the second layer.
摘要翻译： 提供了通过使用纵横比捕获和外延层过度生长来形成衬底上的器件的方法和结构，包括例如晶格失配的材料。 一种方法包括在设置在包括第一半导体材料的基板上的掩模层中形成开口。 在开口内形成包括与第一半导体材料晶格失配的第二半导体材料的第一层。 第一层具有足以在掩模层的顶表面上方延伸的厚度。 包括第二半导体材料的第二层形成在第一层上并且在掩模层的至少一部分之上。 第一层的垂直生长速率大于第一层的横向生长速率，第二层的横向生长速率大于第二层的垂直生长速率。
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2.发明申请Semiconductor Sensor Structures with Reduced Dislocation Defect Densities and Related Methods for the Same 有权具有减少位错缺陷密度的半导体传感器结构及其相关方法公开(公告)号：US20130029449A1
公开(公告)日：2013-01-31
申请号：US13594519
申请日：2012-08-24
IPC分类号： H01L31/18
CPC分类号： H01L27/14689 , H01L21/02381 , H01L21/02521 , H01L21/02532 , H01L21/02639 , H01L21/02647 , H01L21/76224 , H01L27/1446 , H01L27/14612 , H01L27/14643 , H01L31/0304 , H01L31/03046 , H01L31/0312 , H01L31/103 , H01L31/1037 , H01L31/105 , Y02E10/544 , Y02P70/521
摘要： Non-silicon based semiconductor devices are integrated into silicon fabrication processes by using aspect-ratio-trapping materials. Non-silicon light-sensing devices in a least a portion of a crystalline material can output electrons generated by light absorption therein. Exemplary light-sensing devices can have relatively large micron dimensions. As an exemplary application, complementary-metal-oxide-semiconductor photodetectors are formed on a silicon substrate by incorporating an aspect-ratio-trapping technique.
摘要翻译： 非硅基半导体器件通过使用纵横比捕获材料集成到硅制造工艺中。 在结晶材料的至少一部分中的非硅光感测装置可以输出由其中的光吸收产生的电子。 示例性的光感测装置可以具有相对较大的微米尺寸。 作为示例性应用，通过结合纵横比捕获技术在硅衬底上形成互补金属氧化物半导体光电探测器。
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3.发明授权公开(公告)号：US08253211B2
公开(公告)日：2012-08-28
申请号：US12565863
申请日：2009-09-24
IPC分类号： H01L21/14
CPC分类号： H01L27/14689 , H01L21/02381 , H01L21/02521 , H01L21/02532 , H01L21/02639 , H01L21/02647 , H01L21/76224 , H01L27/1446 , H01L27/14612 , H01L27/14643 , H01L31/0304 , H01L31/03046 , H01L31/0312 , H01L31/103 , H01L31/1037 , H01L31/105 , Y02E10/544 , Y02P70/521
摘要： Non-silicon based semiconductor devices are integrated into silicon fabrication processes by using aspect-ratio-trapping materials. Non-silicon light-sensing devices in a least a portion of a crystalline material can output electrons generated by light absorption therein. Exemplary light-sensing devices can have relatively large micron dimensions. As an exemplary application, complementary-metal-oxide-semiconductor photodetectors are formed on a silicon substrate by incorporating an aspect-ratio-trapping technique.
摘要翻译： 非硅基半导体器件通过使用纵横比捕获材料集成到硅制造工艺中。 在结晶材料的至少一部分中的非硅光感测装置可以输出由其中的光吸收产生的电子。 示例性的光感测装置可以具有相对较大的微米尺寸。 作为示例性应用，通过结合纵横比捕获技术在硅衬底上形成互补金属氧化物半导体光电探测器。
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公开(公告)号：US20100072515A1
公开(公告)日：2010-03-25
申请号：US12562206
申请日：2009-09-18
申请人： Ji-Soo Park , James G. Fiorenza
发明人： Ji-Soo Park , James G. Fiorenza
CPC分类号： H01L21/02532 , H01L21/02057 , H01L21/02381 , H01L21/02494 , H01L21/02538 , H01L21/02551 , H01L21/0262 , H01L21/02636 , H01L21/02658 , H01L21/02694 , H01L29/161 , H01L29/165 , H01L29/32
摘要： A surface of the first semiconductor crystalline material has a reduced roughness. A semiconductor device includes a low defect, strained second semiconductor crystalline material over the surface of the first crystalline material. A surface of the strained second semiconductor crystalline material has a reduced roughness. One example includes obtaining a surface with reduced roughness by creating process parameters that reduce impurities at an interfacial boundary between the first and second semiconductor crystalline materials. In one embodiment, the first semiconductor crystalline material can be confined by an opening in an insulator having an aspect ratio sufficient to trap defects using Aspect Ratio Trapping techniques.
摘要翻译： 第一半导体结晶材料的表面具有减小的粗糙度。 半导体器件包括在第一晶体材料的表面上的低缺陷，应变的第二半导体晶体材料。 应变的第二半导体晶体材料的表面具有减小的粗糙度。 一个实例包括通过产生减少在第一和第二半导体晶体材料之间的界面边界处的杂质的工艺参数来获得具有减小的粗糙度的表面。 在一个实施例中，第一半导体晶体材料可以通过绝缘体中的开口限制，该绝缘体具有足以利用纵横比捕获技术捕获缺陷的纵横比。
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5.发明申请SEMICONDUCTOR SENSOR STRUCTURES WITH REDUCED DISLOCATION DEFECT DENSITIES AND RELATED METHODS FOR THE SAME 有权具有减少偏差缺陷密度的半导体传感器结构及其相关方法公开(公告)号：US20100078680A1
公开(公告)日：2010-04-01
申请号：US12565863
申请日：2009-09-24
IPC分类号： H01L31/112 , H01L31/18 , H01L31/0248
CPC分类号： H01L27/14689 , H01L21/02381 , H01L21/02521 , H01L21/02532 , H01L21/02639 , H01L21/02647 , H01L21/76224 , H01L27/1446 , H01L27/14612 , H01L27/14643 , H01L31/0304 , H01L31/03046 , H01L31/0312 , H01L31/103 , H01L31/1037 , H01L31/105 , Y02E10/544 , Y02P70/521
摘要： Non-silicon based semiconductor devices are integrated into silicon fabrication processes by using aspect-ratio-trapping materials. Non-silicon light-sensing devices in a least a portion of a crystalline material can output electrons generated by light absorption therein. Exemplary light-sensing devices can have relatively large micron dimensions. As an exemplary application, complementary-metal-oxide-semiconductor photodetectors are formed on a silicon substrate by incorporating an aspect-ratio-trapping technique.
摘要翻译： 非硅基半导体器件通过使用纵横比捕获材料集成到硅制造工艺中。 在结晶材料的至少一部分中的非硅光感测装置可以输出由其中的光吸收产生的电子。 示例性的光感测装置可以具有相对较大的微米尺寸。 作为示例性应用，通过结合纵横比捕获技术在硅衬底上形成互补金属氧化物半导体光电探测器。
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公开(公告)号：US20190165032A1
公开(公告)日：2019-05-30
申请号：US16204424
申请日：2018-11-29
IPC分类号： H01L27/146 , H01L31/0368 , H01L31/105 , H01L31/108 , H01L31/032
摘要： A photodetector having a substrate, a layer gallium nitride based material supported by the substrate, and a pair of electrodes formed by a two-dimensional electron gas at an interface between the layer gallium nitride based material and a barrier layer, the pair of electrodes being substantially transparent to ultraviolet
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公开(公告)号：US20100012976A1
公开(公告)日：2010-01-21
申请号：US12503597
申请日：2009-07-15
IPC分类号： H01L29/267 , H01L21/20 , H01L29/04
CPC分类号： H01L21/30625 , H01L21/02057 , H01L21/02063 , H01L21/02065 , H01L21/02381 , H01L21/0243 , H01L21/02433 , H01L21/02488 , H01L21/02494 , H01L21/02532 , H01L21/02538 , H01L21/0262 , H01L21/02639 , H01L21/28255 , H01L21/28264 , H01L21/30604 , H01L21/31053 , H01L21/31055
摘要： A device includes a crystalline material within an area confined by an insulator. A surface of the crystalline material has a reduced roughness. One example includes obtaining a surface with reduced roughness by using a planarization process configured with a selectivity of the crystalline material to the insulator greater than one. In a preferred embodiment, the planarization process uses a composition including abrasive spherical silica, H2O2 and water. In a preferred embodiment, the area confined by the insulator is an opening in the insulator having an aspect ratio sufficient to trap defects using an ART technique.
摘要翻译： 一种器件包括在由绝缘体限制的区域内的结晶材料。 结晶材料的表面具有减小的粗糙度。 一个实例包括通过使用配置有大于1的结晶材料对绝缘体的选择性的平坦化工艺来获得具有减小的粗糙度的表面。 在优选的实施方案中，平坦化方法使用包括研磨球形二氧化硅，H 2 O 2和水的组合物。 在优选实施例中，由绝缘体限制的区域是具有足以使用ART技术捕获缺陷的纵横比的绝缘体中的开口。
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公开(公告)号：US20180331186A1
公开(公告)日：2018-11-15
申请号：US15975917
申请日：2018-05-10
IPC分类号： H01L29/205 , H01L29/20 , H01L29/778 , H01L21/02 , H01L29/66
CPC分类号： H01L29/205 , H01L21/0254 , H01L29/2003 , H01L29/66462 , H01L29/778
摘要： A semiconductor device includes a layer of a first semiconducting material, where the first semiconducting material is epitaxially grown to have a crystal structure of a first substrate. The semiconductor device further includes a layer of a second semiconducting material disposed adjacent to the layer of the first semiconducting material to form a heterojunction with the layer of the first semiconducting material. The semiconductor device further includes a first component that is electrically coupled to the heterojunction, and a second substrate that is bonded to the layer of the first semiconducting material.
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公开(公告)号：US08981427B2
公开(公告)日：2015-03-17
申请号：US12503597
申请日：2009-07-15
IPC分类号： H01L21/02 , H01L21/306 , H01L21/28
CPC分类号： H01L21/30625 , H01L21/02057 , H01L21/02063 , H01L21/02065 , H01L21/02381 , H01L21/0243 , H01L21/02433 , H01L21/02488 , H01L21/02494 , H01L21/02532 , H01L21/02538 , H01L21/0262 , H01L21/02639 , H01L21/28255 , H01L21/28264 , H01L21/30604 , H01L21/31053 , H01L21/31055
摘要： A device includes a crystalline material within an area confined by an insulator. A surface of the crystalline material has a reduced roughness. One example includes obtaining a surface with reduced roughness by using a planarization process configured with a selectivity of the crystalline material to the insulator greater than one. In a preferred embodiment, the planarization process uses a composition including abrasive spherical silica, H2O2 and water. In a preferred embodiment, the area confined by the insulator is an opening in the insulator having an aspect ratio sufficient to trap defects using an ART technique.
摘要翻译： 一种器件包括在由绝缘体限制的区域内的结晶材料。 结晶材料的表面具有减小的粗糙度。 一个实例包括通过使用配置有大于1的结晶材料对绝缘体的选择性的平坦化工艺来获得具有减小的粗糙度的表面。 在优选的实施方案中，平坦化方法使用包括研磨球形二氧化硅，H 2 O 2和水的组合物。 在优选实施例中，由绝缘体限制的区域是具有足以使用ART技术捕获缺陷的纵横比的绝缘体中的开口。
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