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    Second Level Interconnect Structures and Methods of Making the Same
    2.
    发明申请
    Second Level Interconnect Structures and Methods of Making the Same 有权
    二级互连结构及其制作方法

    公开(公告)号：US20130270695A1

    公开(公告)日：2013-10-17

    申请号：US13825815

    申请日：2011-09-20

    申请人： Pulugurtha Markondeya Raj ,  Nitesh Kumbhat ,  Venky Sundaraman ,  Rao R. Tummala ,  Xian Qin

    发明人： Pulugurtha Markondeya Raj ,  Nitesh Kumbhat ,  Venky Sundaraman ,  Rao R. Tummala ,  Xian Qin

    IPC分类号： H01L23/00

    CPC分类号： H01L24/16 ,  H01L24/11 ,  H01L2224/16225 ,  H01L2924/14 ,  H01L2924/181 ,  H05K1/0271 ,  H05K3/3436 ,  H05K3/4007 ,  Y02P70/613 ,  H01L2924/00012 ,  H01L2924/00

    摘要： The various embodiments of the present invention provide a stress-relieving, second-level interconnect structure that is low-cost and accommodates TCE mismatch between low-TCE packages and PCBs. The various embodiments of the interconnect structure are reworkable and can be scaled to pitches from about 1 millimeter (mm) to about 150 micrometers (μm). The interconnect structure comprises at least a first pad, a supporting pillar, and a solder bump, wherein the first pad and supporting pillar are operative to absorb substantially all plastic strain, therefore enhancing compliance between the two electronic components. The versatility, scalability, and stress-relieving properties of the interconnect structure of the present invention make it a desirable structure to utilize in current two-dimensional and ever-evolving three-dimensional IC structures.

    摘要翻译： 本发明的各种实施例提供了一种应力消除的二级互连结构，其低成本并且适应低TCE封装和PCB之间的TCE不匹配。 互连结构的各种实施例是可再加工的，并且可以缩放到约1毫米（mm）至约150微米（母体）的间距。 所述互连结构至少包括第一焊盘，支撑柱和焊料凸块，其中所述第一焊盘和支撑柱可操作以吸收基本上所有的塑性应变，从而提高所述两个电子部件之间的顺应性。 本发明的互连结构的多功能性，可扩展性和应力消除特性使其成为在目前的二维和不断发展的三维IC结构中使用的理想结构。

    Ink jet nozzle structures
    6.
    发明授权
    Ink jet nozzle structures 失效
    喷墨喷嘴结构

    公开(公告)号：US4122460A

    公开(公告)日：1978-10-24

    申请号：US823253

    申请日：1977-08-10

    申请人： James N. Humenik ,  Jimmie L. Powell ,  Rao R. Tummala

    发明人： James N. Humenik ,  Jimmie L. Powell ,  Rao R. Tummala

    IPC分类号： B41J2/135 ,  B41J2/16 ,  C03C3/076 ,  C03C3/087 ,  C03C3/089 ,  C03C3/091 ,  C03C4/20 ,  G01D15/18 ,  C03C13/00 ,  C03C27/00

    CPC分类号： B41J2/1632 ,  B41J2/162 ,  B41J2/1623 ,  C03C3/076 ,  C03C3/087 ,  C03C3/089 ,  C03C3/091 ,  C03C4/20

    摘要： The lifetime of multiple capillary nozzle assemblies embedded in a glass mass, of a multiple nozzle ink-jet printer, can be increased and the thermal and mechanical compatibility of the resulting package enhanced by fabrication of the nozzles from glass compositions comprised of SiO.sub.2, ZrO.sub.2, Na.sub.2 O, K.sub.2 O and MgO. Inclusion of ZrO.sub.2 as well as minor amounts of BaO, MgO, CaO, and Al.sub.2 O.sub.3 enhances the alkali resistance of the glass nozzles. Also, the high SiO.sub.2 content of the glasses combined with the presence of ZrO.sub.2, MgO, CaO, and Al.sub.2 O.sub.3 imparts an acid resistance to the nozzles.

    摘要翻译： 可以增加嵌入在多喷嘴喷墨打印机的玻璃块中的多个毛细管喷嘴组件的寿命，并且通过从由SiO 2，ZrO 2，ZrO 2等组成的玻璃组合物制造喷嘴来增强所得包装的热和机械相容性， Na2O，K2O和MgO。 包含ZrO 2以及少量的BaO，MgO，CaO和Al 2 O 3可提高玻璃喷嘴的耐碱性。 此外，玻璃的高SiO 2含量与ZrO 2，MgO，CaO和Al 2 O 3的存在相结合，赋予喷嘴耐酸性。

    HIGH-ASPECT-RATIO METAL-POLYMER COMPOSITE STRUCTURES FOR NANO INTERCONNECTS
    9.
    发明申请
    HIGH-ASPECT-RATIO METAL-POLYMER COMPOSITE STRUCTURES FOR NANO INTERCONNECTS 失效
    用于纳米互连的高比例金属聚合物复合结构

    公开(公告)号：US20080136035A1

    公开(公告)日：2008-06-12

    申请号：US11845384

    申请日：2007-08-27

    申请人： Ankur Aggarwal ,  Pulugurtha Markondeya Raj ,  Rao R. Tummala

    发明人： Ankur Aggarwal ,  Pulugurtha Markondeya Raj ,  Rao R. Tummala

    IPC分类号： H01L23/48

    CPC分类号： B81C1/00619 ,  Y10S977/888 ,  Y10S977/89

    摘要： A low-temperature process that combines high-aspect-ratio polymer structures with electroless copper plating to create laterally compliant MEMS structures. These structures can be used as IC-package interconnects that can lead to reliable, low-cost and high-performance nano wafer-level packaging. High-aspect-ratio low CTE polyimide structures with low stress, high toughness and strength were fabricated using plasma etching. The dry etching process was tuned to yield a wall angle above 80 degrees leading to an aspect ratio higher than 4. The etching process also leads to roughened sidewalls for selective electroless plating on the sidewalls of the polymer structures. These fabricated structures show reduction in the stresses at the interfaces and superior reliability as IC-package nano interconnects. Metal-coated polymer structures from MEMS fabrication techniques can provide low-cost high-performance solutions for wafer-level-packaging. Other embodiments are also claimed and described.

    摘要翻译： 将高纵横比聚合物结构与无电镀铜结合在一起的低温工艺，以制造横向兼容的MEMS结构。 这些结构可用作IC封装互连，可以导致可靠，低成本和高性能的纳米晶圆级封装。 使用等离子体蚀刻制造具有低应力，高韧性和强度的高纵横比低CTE聚酰亚胺结构。 调整干蚀刻工艺以产生高于80度的壁角，导致高于4的纵横比。蚀刻工艺还导致在聚合物结构的侧壁上进行选择性无电镀的粗糙化侧壁。 这些制造的结构显示了作为IC封装纳米互连的界面处的应力减小和优异的可靠性。 来自MEMS制造技术的金属涂层聚合物结构可为晶圆级封装提供低成本的高性能解决方案。 还要求保护和描述其它实施例。

    Ceramic substrate having a protective coating thereon and a method for protecting a ceramic substrate
    10.
    发明授权
    Ceramic substrate having a protective coating thereon and a method for protecting a ceramic substrate 失效
    具有保护涂层的陶瓷基板和保护陶瓷基板的方法

    公开(公告)号：US5196251A

    公开(公告)日：1993-03-23

    申请号：US693746

    申请日：1991-04-30

    申请人： Nanik Bakhru ,  Richard A. Bates ,  George Czornyj ,  Nunzio DiPaolo ,  Ananda H. Kumar ,  Suryanarayana Mukkavilli ,  Heinz O. Steimel ,  Rao R. Tummala

    发明人： Nanik Bakhru ,  Richard A. Bates ,  George Czornyj ,  Nunzio DiPaolo ,  Ananda H. Kumar ,  Suryanarayana Mukkavilli ,  Heinz O. Steimel ,  Rao R. Tummala

    IPC分类号： H01L23/50 ,  H01L21/48 ,  H01L23/12 ,  H01L23/498 ,  H05K3/28

    CPC分类号： H01L23/49811 ,  H01L21/481 ,  H01L21/4853 ,  H01L2924/0002 ,  H01L2924/09701 ,  Y10S428/901 ,  Y10T428/239 ,  Y10T428/24802 ,  Y10T428/24917

    摘要： Disclosed is a ceramic substrate having a protective coating on at least one surface thereof which includes:a ceramic substrate having at least one electrically conductive via extending to a surface of the substrate;an electrically conductive I/O pad electrically connected to at least one of the vias;an I/O pin brazed to the I/O pad, the brazed pin having a braze fillet; anda protective layer of polymeric material fully encapsulating the I/O pad, wherein the layer of polymeric material protects the I/O pad from corrosion.Also disclosed is a method of protecting a ceramic substrate from corrosion, the ceramic substrate of the type having a plurality of electrically conductive vias extending to a surface of the substrate, a multilayer metallic I/O pad electrically connected to at least one of the vias, and an I/O pin brazed to the I/O pad, the brazed pin having a braze fillet, the method comprising the step of:encapsulating fully the I/O pad with a protective layer of polymeric material, wherein the layer of polymeric material protects the I/O pad from corrosion.In a preferred embodiment, the I/O pin is selectively exposed to plasma ashing to remove any errant polymeric material from the pin shank, thereby assuring electrical contact to the pin shank.

    摘要翻译： 公开了一种在其至少一个表面上具有保护涂层的陶瓷衬底，其包括：陶瓷衬底，其具有延伸到衬底的表面的至少一个导电通孔; 电连接到所述通孔中的至少一个的导电I / O焊盘; 钎焊到I / O焊盘的I / O引脚，钎焊引脚具有钎焊焊丝; 以及完全封装I / O焊盘的聚合材料的保护层，其中聚合物材料层保护I / O焊盘免受腐蚀。 还公开了一种保护陶瓷衬底免受腐蚀的方法，该陶瓷衬底具有延伸到衬底表面的多个导电通孔，电连接到至少一个通孔的多层金属I / O焊盘 以及钎焊到I / O焊盘的I / O引脚，钎焊引脚具有钎焊焊丝，该方法包括以下步骤：将I / O焊盘完全封装在聚合材料的保护层上，其中聚合物层 材料保护I / O垫免受腐蚀。 在优选实施例中，I / O销选择性地暴露于等离子体灰化以从销柄移除任何错误的聚合材料，从而确保与销柄的电接触。