公开(公告)号：US07795139B2

公开(公告)日：2010-09-14

申请号：US11777388

申请日：2007-07-13

申请人： Kwon Whan Han ,  Chang Jun Park ,  Min Suk Suh ,  Seong Cheol Kim ,  Sung Min Kim ,  Seung Taek Yang ,  Seung Hyun Lee ,  Jong Hoon Kim ,  Ha Na Lee

发明人： Kwon Whan Han ,  Chang Jun Park ,  Min Suk Suh ,  Seong Cheol Kim ,  Sung Min Kim ,  Seung Taek Yang ,  Seung Hyun Lee ,  Jong Hoon Kim ,  Ha Na Lee

IPC分类号： H01L21/4763

CPC分类号： H01L21/76898 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/16145 ,  H01L2224/274 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/013

摘要： A method for manufacturing a semiconductor package includes forming a groove in the portion outside of the bonding pad of a semiconductor chip provided with the bonding pad on an upper surface thereof; forming an insulation layer on the side wall of the groove; forming a metal layer over the semiconductor chip so as to fill the groove formed with the insulation layer; etching the metal layer to simultaneously form a through silicon via for filling the groove and a distribution layer for connecting the through silicon via and the bonding pad; and removing a rear surface of the semiconductor chip such that the lower surface of the through silicon via protrudes from the semiconductor chip.

摘要翻译： 一种半导体封装的制造方法，其特征在于，在设置有所述接合焊盘的半导体芯片的焊盘的外侧的部分的外表面形成有槽， 在所述槽的侧壁上形成绝缘层; 在半导体芯片上形成金属层，以填充形成有绝缘层的槽; 蚀刻金属层以同时形成用于填充槽的通过硅通孔和用于连接通过硅通孔和接合焊盘的分布层; 以及去除所述半导体芯片的后表面，使得所述贯穿硅通孔的下表面从所述半导体芯片突出。

公开(公告)号：US07446405B2

公开(公告)日：2008-11-04

申请号：US11648281

申请日：2006-12-29

申请人： Jong Hoon Kim ,  Min Suk Suh ,  Chang Jun Park ,  Kwon Whan Han ,  Seong Cheol Kim

发明人： Jong Hoon Kim ,  Min Suk Suh ,  Chang Jun Park ,  Kwon Whan Han ,  Seong Cheol Kim

IPC分类号： H01L23/48

CPC分类号： H01L23/3114 ,  H01L23/3171 ,  H01L2224/05026 ,  H01L2224/05548 ,  H01L2224/056 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/3511 ,  H01L2224/05099

摘要： A wafer level chip scale package includes a semiconductor chip having a plurality of pads; a lower insulation layer having a high Young's modulus of 1˜5 GPa formed on the semiconductor chip to expose the plurality of pads; a plurality of metal patterns formed on the lower insulation layer to be connected to the respective pads; an upper insulation layer having a high Young's modulus of 1˜5 GPa formed on the lower insulation layer and the metal patterns to partially expose the metal patterns; and a plurality of solder balls formed on exposed portions of the metal patterns.

摘要翻译： 晶片级芯片级封装包括具有多个焊盘的半导体芯片; 在半导体芯片上形成的具有1〜5GPa的高杨氏模量的下部绝缘层，以露出多个焊盘; 多个金属图案形成在下绝缘层上以连接到相应的焊盘; 形成在下绝缘层上的具有1〜5GPa的高杨氏模量的上绝缘层和金属图案以部分地暴露金属图案; 以及形成在金属图案的暴露部分上的多个焊球。

公开(公告)号：US20070182022A1

公开(公告)日：2007-08-09

申请号：US11648281

申请日：2006-12-29

申请人： Jong Hoon Kim ,  Min Suk Suh ,  Chang Jun Park ,  Kwon Whan Han ,  Seong Cheol Kim

发明人： Jong Hoon Kim ,  Min Suk Suh ,  Chang Jun Park ,  Kwon Whan Han ,  Seong Cheol Kim

IPC分类号： H01L23/48

CPC分类号： H01L23/3114 ,  H01L23/3171 ,  H01L2224/05026 ,  H01L2224/05548 ,  H01L2224/056 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/3511 ,  H01L2224/05099

摘要： A wafer level chip scale package includes a semiconductor chip having a plurality of pads; a lower insulation layer having a high Young's modulus of 1˜5 GPa formed on the semiconductor chip to expose the plurality of pads; a plurality of metal patterns formed on the lower insulation layer to be connected to the respective pads; an upper insulation layer having a high Young's modulus of 1˜5 GPa formed on the lower insulation layer and the metal patterns to partially expose the metal patterns; and a plurality of solder balls formed on exposed portions of the metal patterns.

摘要翻译： 晶片级芯片级封装包括具有多个焊盘的半导体芯片; 在半导体芯片上形成的具有1〜5GPa的高杨氏模量的下部绝缘层，以露出多个焊盘; 多个金属图案形成在下绝缘层上以连接到相应的焊盘; 形成在下绝缘层上的具有1〜5GPa的高杨氏模量的上绝缘层和金属图案以部分地暴露金属图案; 以及形成在金属图案的暴露部分上的多个焊球。

公开(公告)号：US08395245B2

公开(公告)日：2013-03-12

申请号：US11953967

申请日：2007-12-11

申请人： Jong Hoon Kim ,  Min Suk Suh ,  Seong Cheol Kim ,  Seung Taek Yang ,  Seung Hyun Lee

发明人： Jong Hoon Kim ,  Min Suk Suh ,  Seong Cheol Kim ,  Seung Taek Yang ,  Seung Hyun Lee

IPC分类号： H01L23/495

CPC分类号： H05K1/141 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2225/107 ,  H01L2225/1088 ,  H01L2225/1094 ,  H05K1/021 ,  H05K1/182 ,  H05K1/183 ,  H05K3/0061 ,  H05K2201/10371 ,  H05K2201/10545 ,  H05K2201/10674 ,  H05K2203/1572

摘要： A semiconductor package module includes a circuit board including a board body having a receiving portion and conductive patterns formed on the board body; a semiconductor package received in the receiving portion and having conductive terminals electrically connected to the conductive patterns and an s semiconductor chip electrically connected to the conductive terminals; and a connection member electrically connecting the conductive patterns and the conductive terminals. In the present invention, after a receiving portion having a receiving space is formed in the board body of a circuit board and a semiconductor package is received in the receiving portion, and a connection terminal of the semiconductor package and a conductive pattern of the board body are electrically connected using a connection member, a plurality of semiconductor packages can be stacked in a single circuit board without increasing the thickness thereby significantly improving data storage capacity and data processing speed of the semiconductor package module.

摘要翻译： 一种半导体封装模块，包括：电路板，包括具有接收部分的基板主体和形成在所述基板主体上的导电图案; 接收在所述接收部分中并且具有电连接到所述导电图案的导电端子和与所述导电端子电连接的半导体芯片的半导体封装; 以及电连接导电图案和导电端子的连接构件。 在本发明中，在电路基板的基板主体中形成具有接收空间的接收部分，并且在接收部分中接收半导体封装的接收部分，以及半导体封装的连接端子和板体的导电图案 使用连接构件电连接，多个半导体封装可以堆叠在单个电路板中而不增加厚度，从而显着提高半导体封装模块的数据存储容量和数据处理速度。

公开(公告)号：US20090189267A1

公开(公告)日：2009-07-30

申请号：US12059308

申请日：2008-03-31

申请人： Sung Min Kim ,  Chang Jun Park ,  Kwon Whan Han ,  Seong Cheol Kim ,  Ha Na Lee

发明人： Sung Min Kim ,  Chang Jun Park ,  Kwon Whan Han ,  Seong Cheol Kim ,  Ha Na Lee

IPC分类号： H01L23/02 ,  H01L23/52

CPC分类号： H01L23/50 ,  H01L24/05 ,  H01L24/06 ,  H01L24/14 ,  H01L24/17 ,  H01L25/0657 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/0554 ,  H01L2224/05552 ,  H01L2224/06051 ,  H01L2224/06165 ,  H01L2224/06167 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2924/0001 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/13099

摘要： A semiconductor chip with a chip selection structure suitable for a stacked semiconductor chip includes a semiconductor chip body and a chip selection structure. The chip selection structure includes a chip selection pad disposed over the semiconductor chip body, a main through electrode electrically connected to the chip selection pad, and a sub through electrode interposed between the main through electrode and the chip selection pad. A plurality of the semiconductor chips, each having the same chip selection structure, can be stacked by offsetting the stacked semiconductor chips.

摘要翻译： 具有适合堆叠半导体芯片的芯片选择结构的半导体芯片包括半导体芯片体和芯片选择结构。 芯片选择结构包括设置在半导体芯片主体上的芯片选择焊盘，电连接到芯片选择焊盘的主通孔以及置于主通孔和芯片选择焊盘之间的副通孔。 可以通过抵消堆叠的半导体芯片来堆叠各自具有相同芯片选择结构的多个半导体芯片。

公开(公告)号：US08338921B2

公开(公告)日：2012-12-25

申请号：US13289365

申请日：2011-11-04

申请人： Chang Jun Park ,  Kwon Whan Han ,  Seong Cheol Kim ,  Sung Min Kim ,  Hyeong Seok Choi ,  Ha Na Lee ,  Tac Keun Oh ,  Sang Joon Lim

发明人： Chang Jun Park ,  Kwon Whan Han ,  Seong Cheol Kim ,  Sung Min Kim ,  Hyeong Seok Choi ,  Ha Na Lee ,  Tac Keun Oh ,  Sang Joon Lim

IPC分类号： H01L23/48 ,  H01L21/28

CPC分类号： H01L21/486 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/367 ,  H01L23/552 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/94 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01059 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/3025 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00

摘要： A wafer level chip scale package having an enhanced heat exchange efficiency with an EMF shield is presented. The wafer level chip scale package includes a semiconductor chip, an insulation layer, and a metal plate. The semiconductor chip has a plurality of bonding pads on an upper face thereof. The insulation layer is disposed over the upper face of the semiconductor chip and has openings that expose some portions of the bonding pads. The metal plate covers an upper face of the insulation layer and side faces of the semiconductor chip in which the metal plate is electrically insulated from the bonding pads.

摘要翻译： 提出了具有增强的EMF屏蔽的热交换效率的晶片级芯片级封装。 晶片级芯片级封装包括半导体芯片，绝缘层和金属板。 半导体芯片在其上表面上具有多个接合焊盘。 绝缘层设置在半导体芯片的上表面上，并且具有暴露接合焊盘的一些部分的开口。 金属板覆盖绝缘层的上表面和半导体芯片的侧面，其中金属板与接合焊盘电绝缘。

公开(公告)号：US07859102B2

公开(公告)日：2010-12-28

申请号：US12048304

申请日：2008-03-14

申请人： Sung Min Kim ,  Chang Jun Park ,  Kwon Whan Han ,  Seong Cheol Kim ,  Hyeong Seok Choi ,  Ha Na Lee

发明人： Sung Min Kim ,  Chang Jun Park ,  Kwon Whan Han ,  Seong Cheol Kim ,  Hyeong Seok Choi ,  Ha Na Lee

IPC分类号： H01L23/36

CPC分类号： H01L25/0657 ,  H01L25/0652 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2224/05599

摘要： A stacked wafer level semiconductor package module includes a semiconductor chip module including first and second semiconductor chips each having a rectangular shape. The first semiconductor chip has first pads disposed along a first short side of a lower surface thereof. The second semiconductor chip has second pads disposed along a first short side of a lower surface thereof. The first and second semiconductor chips are stacked so as to expose the first pad and the second pad on one side of the stacked first and second semiconductor chips. The package also includes a substrate having a first connection pad facing the first pad and a second connection pad facing the second pad. The package also includes a first connection member for connecting the first pad to the first connection pad, and a second connection member for connecting the second pad to the second connection pad.

摘要翻译： 堆叠的晶片级半导体封装模块包括半导体芯片模块，其包括具有矩形形状的第一和第二半导体芯片。 第一半导体芯片具有沿其下表面的第一短边设置的第一焊盘。 第二半导体芯片具有沿其下表面的第一短边设置的第二焊盘。 第一和第二半导体芯片被堆叠以便在叠置的第一和第二半导体芯片的一侧上露出第一焊盘和第二焊盘。 封装还包括具有面向第一焊盘的第一连接焊盘和面向第二焊盘的第二连接焊盘的衬底。 该包装还包括用于将第一垫连接到第一连接垫的第一连接构件和用于将第二垫连接到第二连接垫的第二连接构件。

公开(公告)号：US07795073B2

公开(公告)日：2010-09-14

申请号：US12345858

申请日：2008-12-30

申请人： Kwon Whan Han ,  Chang Jun Park ,  Seong Cheol Kim ,  Sung Min Kim ,  Hyeong Seok Choi ,  Ha Na Lee

发明人： Kwon Whan Han ,  Chang Jun Park ,  Seong Cheol Kim ,  Sung Min Kim ,  Hyeong Seok Choi ,  Ha Na Lee

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L24/16 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/11 ,  H01L24/17 ,  H01L24/90 ,  H01L24/97 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/05001 ,  H01L2224/05548 ,  H01L2224/13009 ,  H01L2224/13099 ,  H01L2224/90 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014

摘要： Manufacturing a wafer level stack package includes the steps of back-grinding a lower surface of a wafer including a plurality of first semiconductor chips. A support member is attached to a lower surface of the back-grinded wafer. One or more second semiconductor chips are stacked on the respective first semiconductor chips of the back-grinded wafer. First through-electrodes are formed to electrically connect the stacked first semiconductor chips and second semiconductor chips. Third semiconductor chips are attached to uppermost ones of the stacked second semiconductor chips, and the third semiconductor chips have second through-electrodes which are electrically connected to the first through-electrodes and re-distribution lines which are connected to the second through-electrodes. Outside connection terminals are attached to the re-distribution lines of the third semiconductor chips. The first semiconductor chips of a wafer level on which the second and third semiconductor chips are stacked are sawed to for semiconductor packages at a chip level.

摘要翻译： 制造晶片级堆叠封装包括对包括多个第一半导体芯片的晶片的下表面进行背面磨削的步骤。 支撑构件附接到后磨碎晶片的下表面。 一个或多个第二半导体芯片堆叠在背面研磨的晶片的相应的第一半导体芯片上。 形成第一贯通电极以电连接堆叠的第一半导体芯片和第二半导体芯片。 第三半导体芯片附着到堆叠的第二半导体芯片的最上面，并且第三半导体芯片具有与连接到第二贯通电极的第一贯通电极和再分配线电连接的第二贯通电极。 外部连接端子附接到第三半导体芯片的再分配线路。 第二半导体芯片和第三半导体芯片堆叠的晶片级的第一半导体芯片在芯片级被锯切以用于半导体封装。

公开(公告)号：US07898834B2

公开(公告)日：2011-03-01

申请号：US12059308

申请日：2008-03-31

申请人： Sung Min Kim ,  Chang Jun Park ,  Kwon Whan Han ,  Seong Cheol Kim ,  Ha Na Lee

发明人： Sung Min Kim ,  Chang Jun Park ,  Kwon Whan Han ,  Seong Cheol Kim ,  Ha Na Lee

IPC分类号： G11C5/02

CPC分类号： H01L23/50 ,  H01L24/05 ,  H01L24/06 ,  H01L24/14 ,  H01L24/17 ,  H01L25/0657 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/0554 ,  H01L2224/05552 ,  H01L2224/06051 ,  H01L2224/06165 ,  H01L2224/06167 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2924/0001 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/13099

摘要： A semiconductor chip with a chip selection structure suitable for a stacked semiconductor chip includes a semiconductor chip body and a chip selection structure. The chip selection structure includes a chip selection pad disposed over the semiconductor chip body, a main through electrode electrically connected to the chip selection pad, and a sub through electrode interposed between the main through electrode and the chip selection pad. A plurality of the semiconductor chips, each having the same chip selection structure, can be stacked by offsetting the stacked semiconductor chips.

摘要翻译： 具有适合堆叠半导体芯片的芯片选择结构的半导体芯片包括半导体芯片体和芯片选择结构。 芯片选择结构包括设置在半导体芯片主体上的芯片选择焊盘，电连接到芯片选择焊盘的主通孔以及置于主通孔和芯片选择焊盘之间的副通孔。 可以通过抵消堆叠的半导体芯片来堆叠各自具有相同芯片选择结构的多个半导体芯片。

公开(公告)号：US20090166853A1

公开(公告)日：2009-07-02

申请号：US12048304

申请日：2008-03-14

申请人： Sung Min Kim ,  Chang Jun Park ,  Kwon Whan Han ,  Seong Cheol Kim ,  Hyeong Seok Choi ,  Ha Na Lee

发明人： Sung Min Kim ,  Chang Jun Park ,  Kwon Whan Han ,  Seong Cheol Kim ,  Hyeong Seok Choi ,  Ha Na Lee

IPC分类号： H01L23/36

CPC分类号： H01L25/0657 ,  H01L25/0652 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2224/05599

摘要： A stacked wafer level semiconductor package module includes a semiconductor chip module including first and second semiconductor chips each having a rectangular shape. The first semiconductor chip has first pads disposed along a first short side of a lower surface thereof. The second semiconductor chip has second pads disposed along a first short side of a lower surface thereof. The first and second semiconductor chips are stacked so as to expose the first pad and the second pad on one side of the stacked first and second semiconductor chips. The package also includes a substrate having a first connection pad facing the first pad and a second connection pad facing the second pad. The package also includes a first connection member for connecting the first pad to the first connection pad, and a second connection member for connecting the second pad to the second connection pad.

摘要翻译： 堆叠的晶片级半导体封装模块包括半导体芯片模块，其包括具有矩形形状的第一和第二半导体芯片。 第一半导体芯片具有沿其下表面的第一短边设置的第一焊盘。 第二半导体芯片具有沿其下表面的第一短边设置的第二焊盘。 第一和第二半导体芯片被堆叠以便在叠置的第一和第二半导体芯片的一侧上露出第一焊盘和第二焊盘。 封装还包括具有面向第一焊盘的第一连接焊盘和面向第二焊盘的第二连接焊盘的衬底。 该包装还包括用于将第一垫连接到第一连接垫的第一连接构件和用于将第二垫连接到第二连接垫的第二连接构件。