公开(公告)号：US08546925B2

公开(公告)日：2013-10-01

申请号：US13247174

申请日：2011-09-28

申请人： Juan A. Herbsommer ,  Osvaldo J. Lopez ,  Jonathan A. Noquil ,  David Jauregui ,  Mark E. Granahan

发明人： Juan A. Herbsommer ,  Osvaldo J. Lopez ,  Jonathan A. Noquil ,  David Jauregui ,  Mark E. Granahan

IPC分类号： H01L23/02

CPC分类号： H01L24/05 ,  H01L23/36 ,  H01L23/492 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L25/072 ,  H01L2224/0401 ,  H01L2224/05555 ,  H01L2224/05567 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13021 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/14131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2924/01029 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15321 ,  H02M3/1588 ,  Y02B70/1466 ,  H01L2924/01047 ,  H01L2924/00014 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/014 ,  H01L2924/00

摘要： A packaged power supply module (100) comprising a chip (110) with a first power field effect transistor (FET) and a second chip (120) with a second FET conductively attached side-by-side onto a conductive carrier (130), the transistors having bond pads of a first area (210) and the carrier having bond pads of a second area (230) smaller than the first area. Conductive bumps (114, 115, 124, 125) attached to the transistor bond pads and conductive bumps (126) attached to the carrier bond pads have equal volume and are coplanar (150), the bumps on the transistor pads having a first height and the bumps on the carrier pads having a second height greater than the first height.

摘要翻译： 一种封装的电源模块（100），包括具有第一功率场效应晶体管（FET）的芯片（110）和第二芯片（120），其中第二FET导体地并排连接到导电载体（130）上， 所述晶体管具有第一区域（210）的接合焊盘，并且所述载体具有比所述第一区域小的第二区域（230）的接合焊盘。 连接到晶体管接合焊盘的导电凸块（114,115,124,125）和连接到载体接合焊盘的导电凸块（126）具有相等的体积并且是共面的（150），晶体管焊盘上的凸块具有第一高度和 载体垫上的凸起具有大于第一高度的第二高度。

公开(公告)号：US08760872B2

公开(公告)日：2014-06-24

申请号：US13247650

申请日：2011-09-28

申请人： Juan A. Herbsommer ,  Osvaldo J Lopez ,  Jonathan A Noquil ,  David Jauregui ,  Lucian Hriscu

发明人： Juan A. Herbsommer ,  Osvaldo J Lopez ,  Jonathan A Noquil ,  David Jauregui ,  Lucian Hriscu

IPC分类号： H05K7/20

CPC分类号： H02M3/00 ,  H01R43/26 ,  H02B1/48 ,  H05K7/2039 ,  H05K7/2089 ,  H05K7/209 ,  Y10T29/49002 ,  Y10T29/49073 ,  Y10T29/49117

摘要： A power supply converter (100) comprising a first FET (210) connected to ground (230), the first FET coupled to a second FET (220) tied to an input terminal (240), both FETs conductively attached side-by-side to a first surface of a metal carrier (120) and operating as a converter generating heat; and a packaged load inductor (110) tied to the carrier and an output terminal (241), the inductor package wrapped by a metal sleeve (113) in touch with the opposite surface of the metal carrier, the sleeve operable to spread and radiate the heat generated by the converter.

摘要翻译： 一种电源转换器（100），包括连接到地（230）的第一FET（210），所述第一FET耦合到连接到输入端子（240）的第二FET（220），两个FET并排导电地并入 到金属载体（120）的第一表面并作为产生热量的转换器工作; 和连接到所述载体的封装负载电感器（110）和输出端子（241），所述电感器封装件包括与所述金属载体的相对表面接触的金属套筒（113），所述套管可操作以扩展和辐射 由转换器产生的热量。

公开(公告)号：US08431979B2

公开(公告)日：2013-04-30

申请号：US13078112

申请日：2011-04-01

申请人： Juan A Herbsommer ,  Osvaldo J Lopez ,  Jonathan A Noquil ,  David Jauregui

发明人： Juan A Herbsommer ,  Osvaldo J Lopez ,  Jonathan A Noquil ,  David Jauregui

IPC分类号： H01L27/108

CPC分类号： H02M3/00 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49589 ,  H01L23/642 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49111 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

摘要： A power supply module (400) comprising a metal leadframe with a pad (401) and a first metal clip (440) including a plate (440a), an extension (440b) and a ridge (440c); the plate and extension are spaced from the leadframe pad, and the ridge connected to an input supply. A synchronous Buck converter is in the space between the clip plate and the leadframe pad, the converter including a control FET die (410) soldered onto a sync FET die (420), the clip plate soldered to the control die having an input inductance (462), and the sync die soldered to the leadframe pad having an output capacitance. A capacitor (480a, 480b) integrated into the space between the clip extension and the leadframe pad, the clip extension soldered to the capacitor having a desired integrated inductance (463) operable to channel electrical energy from the switch node to ground.

摘要翻译： 一种电源模块（400），包括具有衬垫（401）的金属引线框和包括板（440a），延伸部（440b）和脊（440c）的第一金属夹（440） 板和延伸部与引线框垫间隔开，并且脊连接到输入电源。 同步降压转换器位于夹板和引线框垫之间的空间中，转换器包括焊接到同步FET管芯（420）上的控制FET管芯（410），焊接到控制管芯的夹板具有输入电感（ 462），并且同步模具焊接到具有输出电容的引线框架焊盘。 集成在夹子延伸部分和引线框架垫片之间的空间中的电容器（480a，480b），夹持器延伸焊接到具有期望的集成电感（463）的电容器上，可操作地将电能从开关节点引导到地。

公开(公告)号：US07242169B2

公开(公告)日：2007-07-10

申请号：US11069362

申请日：2005-03-01

申请人： Takashi Kanamori ,  Stephen J. Kim ,  David Jauregui

发明人： Takashi Kanamori ,  Stephen J. Kim ,  David Jauregui

IPC分类号： G05F1/00

CPC分类号： H02M3/157 ,  H02M3/1588 ,  Y02B70/1466

摘要： An apparatus and method for regulating a voltage to a load to compensate for one or more parasitic impedances. A first amplifier measures the voltage drop due to a first parasitic impedance, and a second amplifier measures the voltage drop due to a second parasitic impedance. An offset generator sums the first and second voltage drops with a reference voltage, and drives a DC-to-DC converter to produce an input voltage matching the summed voltages. Accordingly, the voltage at a load between the parasitic impedances matches the reference voltage. The load may be, for example, a computer microprocessor or central processing unit.

摘要翻译： 一种用于调节负载的电压以补偿一个或多个寄生阻抗的装置和方法。 第一放大器测量由于第一寄生阻抗引起的电压降，并且第二放大器测量由于第二寄生阻抗引起的电压降。 偏移发生器将第一和第二电压降与参考电压相加，并驱动DC-DC转换器以产生与求和电压相匹配的输入电压。 因此，寄生阻抗之间的负载电压与参考电压相匹配。 负载可以是例如计算机微处理器或中央处理单元。

公开(公告)号：USRE42658E1

公开(公告)日：2011-08-30

申请号：US11787234

申请日：2007-04-12

申请人： David Jauregui

发明人： David Jauregui

IPC分类号： H05K7/00

CPC分类号： H02M7/003 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12032 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/30107 ,  H02M3/1588 ,  H02M2001/0009 ,  Y02B70/1466 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A multi-chip module (MCM) provides power circuitry on a computer motherboard in a package of reduced size without sacrificing performance. The MCM co-packages essential power circuit components on a ball grid array (BGA) substrate. Two power MOSFETs disposed on the BGA substrate are connected in a half-bridge arrangement between an input voltage and ground. A MOSFET gate driver is electrically connected to respective gate inputs of the two power MOSFETs for alternately switching the power MOSFETs to generate an alternating output voltage at a common output node between the power MOSFETs. At least one Schottky diode is disposed on the BGA substrate and connected between the common output node and ground to minimize losses during deadtime conduction periods. The input capacitor of the circuit is contained within the MCM housing and is located close to the MOSFETs, reducing stray inductance in the circuit. The MCM package is thin and has dimensions of about 1 cm by 1 cm or less.

摘要翻译： 多芯片模块（MCM）在计算机主板上以减小尺寸的封装提供电源电路，而不会牺牲性能。 MCM在球栅阵列（BGA）基板上共同封装基本电源电路组件。 设置在BGA基板上的两个功率MOSFET以输入电压和地之间的半桥布置连接。 MOSFET栅极驱动器电连接到两个功率MOSFET的相应栅极输入，用于交替地切换功率MOSFET以在功率MOSFET之间的公共输出节点处产生交流输出电压。 至少一个肖特基二极管设置在BGA衬底上并连接在公共输出节点和地之间，以最大限度地减少死区时间内的损耗。 电路的输入电容器包含在MCM外壳内，靠近MOSFET，减少了电路中的杂散电感。 MCM封装较薄，尺寸约为1厘米×1厘米或更小。

公开(公告)号：US20060197509A1

公开(公告)日：2006-09-07

申请号：US11069362

申请日：2005-03-01

申请人： Takashi Kanamori ,  Stephen Kim ,  David Jauregui

发明人： Takashi Kanamori ,  Stephen Kim ,  David Jauregui

IPC分类号： G05F1/656 ,  G05F1/10

CPC分类号： H02M3/157 ,  H02M3/1588 ,  Y02B70/1466

摘要： An apparatus and method for regulating a voltage to a load to compensate for one or more parasitic impedances. A first amplifier measures the voltage drop due to a first parasitic impedance, and a second amplifier measures the voltage drop due to a second parasitic impedance. An offset generator sums the first and second voltage drops with a reference voltage, and drives a DC-to-DC converter to produce an input voltage matching the summed voltages. Accordingly, the voltage at a load between the parasitic impedances matches the reference voltage. The load may be, for example, a computer microprocessor or central processing unit.

摘要翻译： 一种用于调节负载的电压以补偿一个或多个寄生阻抗的装置和方法。 第一放大器测量由于第一寄生阻抗引起的电压降，并且第二放大器测量由于第二寄生阻抗引起的电压降。 偏移发生器将第一和第二电压降与参考电压相加，并驱动DC-DC转换器以产生与求和电压相匹配的输入电压。 因此，寄生阻抗之间的负载电压与参考电压相匹配。 负载可以是例如计算机微处理器或中央处理单元。

公开(公告)号：US07098637B2

公开(公告)日：2006-08-29

申请号：US10843165

申请日：2004-05-10

申请人： David Jauregui ,  Jason Zhang

发明人： David Jauregui ,  Jason Zhang

IPC分类号： G05F1/40 ,  H02M7/10

CPC分类号： H02M1/088 ,  G11C5/147 ,  H02M3/156

摘要： An improved active voltage positioning (AVP) implementation for a power supply for a microprocessor or the like includes an AVP circuit which is separated from the power supply error amplifier by a buffer amplifier having a parallel RC feedback circuit to controllably adjust the transient response. An AVP signal derived from an output load current sensing element provides an input to the buffer amplifier. A second input is provided by power supply reference voltage. A output of the buffer amplifier is connected as an input to the error amplifier to provide the AVP window. This permits separate adjustment of the transient behavior of the error loop and the AVP loop.

摘要翻译： 用于微处理器等的电源的改进的有源电压定位（AVP）实现包括AVP电路，其通过具有并联RC反馈电路的缓冲放大器与电源误差放大器分离，以可控地调节瞬态响应。 从输出负载电流检测元件得到的AVP信号向缓冲放大器提供输入。 第二个输入由电源参考电压提供。 缓冲放大器的输出作为输入连接到误差放大器以提供AVP窗口。 这允许单独调整错误循环和AVP循环的瞬态行为。

公开(公告)号：US08866464B2

公开(公告)日：2014-10-21

申请号：US13327146

申请日：2011-12-15

申请人： Scott E. Ragona ,  Rengang Chen ,  David Jauregui

发明人： Scott E. Ragona ,  Rengang Chen ,  David Jauregui

IPC分类号： G05F1/00

CPC分类号： H02M3/1588 ,  H02M2001/0009 ,  Y02B70/1466

摘要： Systems and methods for regulating a switching converter are disclosed. One embodiment of the present invention relates to a power supply system that includes a switching converter that provides an output voltage by alternately turning on and off a high-side transistor and a low-side transistor both coupled to an output inductor through a switching node. The switching converter includes a drive circuit that regulates the output voltage based on a feedback signal. The power supply system also includes a simulated output generator that generates and provides the drive circuit with a simulated inductor waveform as the feedback signal based on a low-side output waveform of the low-side transistor measured at the switching node during off-times of the switching converter.

摘要翻译： 公开了一种用于调节开关转换器的系统和方法。 本发明的一个实施例涉及一种电源系统，其包括开关转换器，其通过交替地接通和断开通过开关节点耦合到输出电感器的高侧晶体管和低侧晶体管来提供输出电压。 开关转换器包括基于反馈信号来调节输出电压的驱动电路。 电源系统还包括模拟输出发生器，其产生并提供驱动电路，该驱动电路具有仿真电感波形作为反馈信号，该反馈信号基于在断开时间期间在开关节点处测量的低侧晶体管的低侧输出波形 开关转换器。

公开(公告)号：US20100171543A1

公开(公告)日：2010-07-08

申请号：US12350651

申请日：2009-01-08

申请人： Jacek Korec ,  Christopher F. Bull ,  Juan Alejandro Herbsommer ,  David Jauregui ,  Christopher B. Kocon

发明人： Jacek Korec ,  Christopher F. Bull ,  Juan Alejandro Herbsommer ,  David Jauregui ,  Christopher B. Kocon

IPC分类号： H03K17/687 ,  H01L29/94 ,  H01L23/495

CPC分类号： H01L23/49575 ,  H01L23/49524 ,  H01L23/49562 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40139 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/49431 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12036 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30107 ,  H01L2924/3025 ,  H03K17/6871 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A packaged switching device for power applications includes at least one pair of power MOSFET transistor dies connected between upper and lower power source rail leads, a high side one of the pair of MOSFET transistor dies being connected to the upper power source rail lead and a low side one of the pair of MOSFET transistor dies being connected to the lower power source rail lead. At least one of the MOSFET transistor dies is configured for vertical current flow therethrough and has a source electrode at a backside thereof.

摘要翻译： 用于电力应用的封装开关器件包括连接在上部和下部电源轨道引线之间的至少一对功率MOSFET晶体管管芯，该对MOSFET晶体管管芯中的高端一个连接到上部电源轨道引线，并且低 一对MOSFET晶体管管芯中的一侧连接到下部电源轨道引线。 MOSFET晶体管管芯中的至少一个被配置为用于垂直电流流过其中，并且在其背面具有源电极。

公开(公告)号：US06879491B2

公开(公告)日：2005-04-12

申请号：US10252988

申请日：2002-09-23

申请人： David Jauregui

发明人： David Jauregui

IPC分类号： H01L25/18 ,  H01L25/04 ,  H02M3/158 ,  H02M7/00 ,  H05K7/00

CPC分类号： H02M7/003 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12032 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/30107 ,  H02M3/1588 ,  H02M2001/0009 ,  Y02B70/1466 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A multi-chip module (MCM) provides power circuitry on a computer motherboard in a package of reduced size without sacrificing performance. The MCM co-packages essential power circuit components on a ball grid array (BGA) substrate. Two power MOSFETs disposed on the BGA substrate are connected in a half-bridge arrangement between an input voltage and ground. A MOSFET gate driver is electrically connected to respective gate inputs of the two power MOSFETs for alternately switching the power MOSFETs to generate an alternating output voltage at a common output node between the power MOSFETs. At least one Schottky diode is disposed on the BGA substrate and connected between the common output node and ground to minimize losses during deadtime conduction periods. The input capacitor of the circuit is contained within the MCM housing and is located close to the MOSFETs, reducing stray inductance in the circuit. The MCM package is thin and has dimensions of about 1 cm by 1 cm or less.

摘要翻译： 多芯片模块（MCM）在计算机主板上以减小尺寸的封装提供电源电路，而不会牺牲性能。 MCM在球栅阵列（BGA）基板上共同封装基本电源电路组件。 设置在BGA基板上的两个功率MOSFET以输入电压和地之间的半桥布置连接。 MOSFET栅极驱动器电连接到两个功率MOSFET的相应栅极输入，用于交替地切换功率MOSFET以在功率MOSFET之间的公共输出节点处产生交流输出电压。 至少一个肖特基二极管设置在BGA衬底上并连接在公共输出节点和地之间，以最大限度地减少死区时间内的损耗。 电路的输入电容器包含在MCM外壳内，靠近MOSFET，减少了电路中的杂散电感。 MCM封装较薄，尺寸约为1厘米×1厘米或更小。