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公开(公告)号：US20080036078A1
公开(公告)日：2008-02-14
申请号：US11464333
申请日：2006-08-14
CPC分类号： H01L23/49562 , H01L23/49524 , H01L24/37 , H01L24/38 , H01L24/40 , H01L24/41 , H01L2224/32245 , H01L2224/37011 , H01L2224/37147 , H01L2224/40095 , H01L2224/40245 , H01L2224/48247 , H01L2224/73221 , H01L2224/83801 , H01L2224/84801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01023 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01072 , H01L2924/01076 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/10329 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2924/00012 , H01L2924/00014
摘要： A wirebond-less packaged semiconductor device includes a plurality of I/O contacts, at least one semiconductor die, the semiconductor die having a bottom major surface and a top major surface, the top major surface having at least two electrically isolated electrodes, and a conductive clip system disposed over the top major surface, the clip system comprising at least two electrically isolated sections coupling the electrodes to respective I/O contacts.
摘要翻译： 一种无引线封装的半导体器件包括多个I / O触点，至少一个半导体管芯，该半导体管芯具有底部主表面和顶部主表面，该顶部主表面具有至少两个电隔离电极，以及 导电夹系统设置在顶部主表面上，夹子系统包括将电极耦合到相应I / O触点的至少两个电隔离部分。
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公开(公告)号：US08049312B2
公开(公告)日：2011-11-01
申请号：US12352215
申请日：2009-01-12
IPC分类号： H01L23/495 , H01L23/10
CPC分类号： H01L23/4334 , H01L23/49524 , H01L23/49562 , H01L24/37 , H01L24/40 , H01L24/41 , H01L2224/32245 , H01L2224/37011 , H01L2224/37147 , H01L2224/4007 , H01L2224/40095 , H01L2224/40245 , H01L2224/40247 , H01L2224/48247 , H01L2224/73221 , H01L2224/83801 , H01L2224/84801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/13091 , H01L2924/181 , H01L2924/00012
摘要： A semiconductor die package includes: an assembly including a semiconductor die, a clip structure attached to an upper surface of the semiconductor die, and a heat sink attached to an upper surface of the clip structure; and a molding material partially encapsulating the assembly, wherein an upper surface of the heat sink is exposed through the molding material.
摘要翻译： 半导体管芯封装包括：包括半导体管芯，附接到半导体管芯的上表面的夹结构和附接到夹结构的上表面的散热器的组件; 以及部分地封装所述组件的模制材料，其中所述散热器的上表面通过所述模制材料暴露。
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公开(公告)号：US20100176508A1
公开(公告)日：2010-07-15
申请号：US12352215
申请日：2009-01-12
CPC分类号： H01L23/4334 , H01L23/49524 , H01L23/49562 , H01L24/37 , H01L24/40 , H01L24/41 , H01L2224/32245 , H01L2224/37011 , H01L2224/37147 , H01L2224/4007 , H01L2224/40095 , H01L2224/40245 , H01L2224/40247 , H01L2224/48247 , H01L2224/73221 , H01L2224/83801 , H01L2224/84801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/13091 , H01L2924/181 , H01L2924/00012
摘要： A semiconductor die package includes: an assembly including a semiconductor die, a clip structure attached to an upper surface of the semiconductor die, and a heat sink attached to an upper surface of the clip structure; and a molding material partially encapsulating the assembly, wherein an upper surface of the heat sink is exposed through the molding material.
摘要翻译： 半导体管芯封装包括：包括半导体管芯，附接到半导体管芯的上表面的夹结构和附接到夹结构的上表面的散热器的组件; 以及部分地封装所述组件的模制材料，其中所述散热器的上表面通过所述模制材料暴露。
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公开(公告)号：US20110074007A1
公开(公告)日：2011-03-31
申请号：US12569314
申请日：2009-09-29
IPC分类号： H01L23/495 , H01L21/50
CPC分类号： H01L23/49568 , H01L23/3107 , H01L23/49537 , H01L23/49562 , H01L24/34 , H01L2224/32245 , H01L2224/8385 , H01L2224/8485 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2924/00014
摘要： A method and structure for a dual heat dissipating semiconductor device. A method includes attaching a drain region on a first side of a die, such as a power metal oxide semiconductor field effect transistor (MOSFET) to a first leadframe subassembly. A source region and a gate region on a second side of the die are attached to a second leadframe subassembly. The first leadframe subassembly is attached to a third leadframe subassembly, then the device is encapsulated or otherwise packaged. An exposed portion of the first leadframe subassembly provides an external heat sink for the drain region, and the second leadframe subassembly provides external heat sinks for the source region and the gate region, as well as output leads for the gate region. The third leadframe subassembly provides output leads for the drain region.
摘要翻译： 一种双重散热半导体器件的方法和结构。 一种方法包括将诸如功率金属氧化物半导体场效应晶体管（MOSFET）的管芯的第一侧上的漏极区域附接到第一引线框子组件。 模具的第二侧上的源极区域和栅极区域附接到第二引线框架子组件。 第一引线框子组件连接到第三引线框子组件，然后将器件封装或以其它方式封装。 第一引线框子组件的暴露部分提供用于漏区的外部散热器，并且第二引线框子组件为源极区域和栅极区域以及栅极区域的输出引线提供外部散热器。 第三引线框子组件提供漏区的输出引线。
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公开(公告)号：US20100171543A1
公开(公告)日：2010-07-08
申请号：US12350651
申请日：2009-01-08
申请人： Jacek Korec , Christopher F. Bull , Juan Alejandro Herbsommer , David Jauregui , Christopher B. Kocon
发明人： Jacek Korec , Christopher F. Bull , Juan Alejandro Herbsommer , David Jauregui , Christopher B. Kocon
IPC分类号： H03K17/687 , H01L29/94 , H01L23/495
CPC分类号： H01L23/49575 , H01L23/49524 , H01L23/49562 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/37147 , H01L2224/40095 , H01L2224/40137 , H01L2224/40139 , H01L2224/40245 , H01L2224/40247 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/49171 , H01L2224/49431 , H01L2224/73219 , H01L2224/73221 , H01L2224/84801 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/12036 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/30107 , H01L2924/3025 , H03K17/6871 , H01L2924/00 , H01L2224/05599 , H01L2924/00012
摘要： A packaged switching device for power applications includes at least one pair of power MOSFET transistor dies connected between upper and lower power source rail leads, a high side one of the pair of MOSFET transistor dies being connected to the upper power source rail lead and a low side one of the pair of MOSFET transistor dies being connected to the lower power source rail lead. At least one of the MOSFET transistor dies is configured for vertical current flow therethrough and has a source electrode at a backside thereof.
摘要翻译： 用于电力应用的封装开关器件包括连接在上部和下部电源轨道引线之间的至少一对功率MOSFET晶体管管芯，该对MOSFET晶体管管芯中的高端一个连接到上部电源轨道引线，并且低 一对MOSFET晶体管管芯中的一侧连接到下部电源轨道引线。 MOSFET晶体管管芯中的至少一个被配置为用于垂直电流流过其中，并且在其背面具有源电极。
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6.发明申请Vertically Stacked Power FETS and Synchronous Buck Converter Having Low On-Resistance 审中-公开具有低导通电阻的垂直堆叠功率FET和同步降压转换器公开(公告)号：US20140063744A1
公开(公告)日：2014-03-06
申请号：US13603905
申请日：2012-09-05
CPC分类号： H01L23/49575 , H01L23/4334 , H01L23/492 , H01L23/49537 , H01L24/37 , H01L24/40 , H01L24/41 , H01L25/074 , H01L2224/37147 , H01L2224/40095 , H01L2224/40137 , H01L2224/40245 , H01L2224/48091 , H01L2224/48247 , H01L2224/49113 , H01L2224/49171 , H01L2224/73221 , H01L2224/83801 , H01L2224/84801 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A power FET (100) comprising a leadframe including a pad (110), a first lead (111), and a second lead (112); a first metal clip (150) including a plate (150a), an extension (150b) and a ridge (150c), the plate and extension spaced from the leadframe pad and the ridge connected to the pad; a vertically assembled stack of FET chips in the space between the plate and the pad, the stack including a first n-channel FET chip (120) having the drain terminal on one surface and the source and gate terminals on the opposite surface, the drain terminal attached to the pad, the source terminal attached to a second clip (140) tied to the first lead; and a second n-channel FET chip (130) having the source terminal on one surface and the drain and gate terminals on the opposite surface, the source terminal attached to the second clip, its drain terminal attached to the first clip; wherein the drain-source on-resistance of the FET stack is smaller than the on-resistance of the first FET chip and of the second FET chip.
摘要翻译： 一种功率FET（100），包括包括焊盘（110），第一引线（111）和第二引线（112）的引线框架; 包括板（150a），延伸部（150b）和脊（150c）的第一金属夹（150），所述板和延伸部与所述引线框垫间隔开并且连接到所述焊盘; 在板和焊盘之间的空间中垂直组装的FET芯片堆叠，所述堆叠包括在一个表面上具有漏极端子的第一n沟道FET芯片（120），并且在相对表面上具有源极和栅极端子，漏极 端子附接到焊盘，源极端子附接到与第一引线相连的第二夹子（140）; 以及第二n沟道FET芯片，其在一个表面上具有源极端子，在相对表面上具有漏极和栅极端子，源极端子附接到第二夹子，其漏极端子附接到第一夹子; 其中所述FET堆叠的所述漏极 - 源极导通电阻小于所述第一FET芯片和所述第二FET芯片的导通电阻。
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7.发明授权Electroless plating of porous and non-porous nickel layers, and gold layer in semiconductor device 有权多孔和无孔镍层的无电镀，以及半导体器件中的金层公开(公告)号：US08455361B2
公开(公告)日：2013-06-04
申请号：US12943341
申请日：2010-11-10
IPC分类号： H01L21/44
CPC分类号： H01L24/03 , H01L24/05 , H01L2224/03424 , H01L2224/03464 , H01L2224/0401 , H01L2224/04042 , H01L2224/05005 , H01L2224/05016 , H01L2224/05018 , H01L2224/05022 , H01L2224/05073 , H01L2224/05155 , H01L2224/05562 , H01L2224/05568 , H01L2224/05573 , H01L2224/05644 , H01L2224/13099 , H01L2924/00013 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01084 , H01L2924/014 , H01L2924/14 , H01L2924/365 , H01L2924/01028 , H01L2224/05099 , H01L2224/13599 , H01L2224/05599 , H01L2224/29099 , H01L2224/29599 , H01L2224/05552
摘要： A method for maintaining non-porous nickel layer at a nickel/passivation interface of a semiconductor device in a nickel/gold electroless plating process. The method can include sequentially electroless plating of each of the nickel layer and gold layer on the device layer to pre-determined thicknesses to prevent corrosion of the nickel layer from reaching the device layer during the electroless gold plating process.
摘要翻译： 一种用于在镍/金无电镀处理中在半导体器件的镍/钝化界面处维持无孔镍层的方法。 该方法可以包括将器件层上的镍层和金层中的每一个顺序无电镀以预定的厚度，以防止在无电镀金工艺期间镍层的腐蚀到达器件层。
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公开(公告)号：US08354303B2
公开(公告)日：2013-01-15
申请号：US12569314
申请日：2009-09-29
IPC分类号： H01L21/00
CPC分类号： H01L23/49568 , H01L23/3107 , H01L23/49537 , H01L23/49562 , H01L24/34 , H01L2224/32245 , H01L2224/8385 , H01L2224/8485 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2924/00014
摘要： A method and structure for a dual heat dissipating semiconductor device. A method includes attaching a drain region on a first side of a die, such as a power metal oxide semiconductor field effect transistor (MOSFET) to a first leadframe subassembly. A source region and a gate region on a second side of the die are attached to a second leadframe subassembly. The first leadframe subassembly is attached to a third leadframe subassembly, then the device is encapsulated or otherwise packaged. An exposed portion of the first leadframe subassembly provides an external heat sink for the drain region, and the second leadframe subassembly provides external heat sinks for the source region and the gate region, as well as output leads for the gate region. The third leadframe subassembly provides output leads for the drain region.
摘要翻译： 一种双重散热半导体器件的方法和结构。 一种方法包括将诸如功率金属氧化物半导体场效应晶体管（MOSFET）的管芯的第一侧上的漏极区域附接到第一引线框子组件。 模具的第二侧上的源极区域和栅极区域附接到第二引线框架子组件。 第一引线框子组件连接到第三引线框子组件，然后将器件封装或以其它方式封装。 第一引线框子组件的暴露部分提供用于漏区的外部散热器，并且第二引线框子组件为源极区域和栅极区域以及栅极区域的输出引线提供外部散热器。 第三引线框子组件提供漏区的输出引线。
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9.发明申请公开(公告)号：US20110163454A1
公开(公告)日：2011-07-07
申请号：US12943341
申请日：2010-11-10
IPC分类号： H01L23/532 , H01L21/3205
CPC分类号： H01L24/03 , H01L24/05 , H01L2224/03424 , H01L2224/03464 , H01L2224/0401 , H01L2224/04042 , H01L2224/05005 , H01L2224/05016 , H01L2224/05018 , H01L2224/05022 , H01L2224/05073 , H01L2224/05155 , H01L2224/05562 , H01L2224/05568 , H01L2224/05573 , H01L2224/05644 , H01L2224/13099 , H01L2924/00013 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01084 , H01L2924/014 , H01L2924/14 , H01L2924/365 , H01L2924/01028 , H01L2224/05099 , H01L2224/13599 , H01L2224/05599 , H01L2224/29099 , H01L2224/29599 , H01L2224/05552
摘要： A method and resulting device for maintaining non-porous nickel layer at a nickel/passivation interface of a semiconductor device in a nickel/gold electroless plating process. The method can include determining a thickness of a gold layer of the semiconductor device; determining an electroless plating rate and plating time of the gold layer to reach the determined thickness; determining a thickness of nickel under the gold layer to maintain the non-porous nickel layer at the nickel/passivation interface at a termination of an electroless gold plating process; and following the determinations, sequentially electroless plating of each of the nickel layer and gold layer on the device layer to the determined thicknesses.
摘要翻译： 一种用于在镍/金无电镀工艺中在半导体器件的镍/钝化界面处维持无孔镍层的方法和所得装置。 该方法可以包括确定半导体器件的金层的厚度; 确定金层的无电镀电镀速率和电镀时间以达到确定的厚度; 确定金层下方的镍的厚度，以在无电镀金工艺终止时将镍多孔镍层保持在镍/钝化界面处; 并且在确定之后，将器件层上的镍层和金层中的每一个顺序无电镀到所确定的厚度。
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公开(公告)号：US07541220B2
公开(公告)日：2009-06-02
申请号：US11302690
申请日：2005-12-14
申请人： Timothy Brooks Bambridge , Jeffery J. Gilbert , Juan Alejandro Herbsommer , Jeffrey Michael Klemovage , George John Libricz, Jr.
发明人： Timothy Brooks Bambridge , Jeffery J. Gilbert , Juan Alejandro Herbsommer , Jeffrey Michael Klemovage , George John Libricz, Jr.
IPC分类号： H01L21/44
CPC分类号： H01L23/36 , H01L23/047 , H01L23/5387 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/16 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48472 , H01L2224/49175 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/3025 , H01L2924/00014 , H01L2924/00
摘要： An integrated circuit device having a flexible leadframe, and techniques for fabricating the flexible leadframe and integrated circuit device, are provided. In one aspect of the invention, an integrated circuit device comprises a heat spreader having a top surface and a bottom surface. At least one integrated circuit die is attached to the top surface of the heat spreader. A flexible leadframe is also attached to the top surface of the heat spreader. The flexible leadframe has one or more flexible layers, including at least one flexible insulating layer. A plurality of electrically conductive traces are defined on the at least one flexible insulating layer.
摘要翻译： 提供了一种具有柔性引线框架的集成电路器件，以及用于制造柔性引线框和集成电路器件的技术。 在本发明的一个方面，集成电路装置包括具有顶表面和底表面的散热器。 至少一个集成电路管芯连接到散热器的顶表面。 柔性引线框架也附接到散热器的顶表面。 柔性引线框具有一个或多个柔性层，包括至少一个柔性绝缘层。 多个导电迹线限定在至少一个柔性绝缘层上。
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