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公开(公告)号:US20070194454A1
公开(公告)日:2007-08-23
申请号:US11626286
申请日:2007-01-23
IPC分类号: H01L23/52
CPC分类号: H01L25/18 , G11C5/06 , H01L24/45 , H01L24/73 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48145 , H01L2224/48147 , H01L2224/48227 , H01L2224/49171 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06555 , H01L2225/06562 , H01L2225/06586 , H01L2924/01014 , H01L2924/01037 , H01L2924/01079 , H01L2924/10253 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要: This invention is to provide a nonvolatile memory device that enhances a size reduction and mass productivity while ensuring reliability and signal transmission performance. A nonvolatile memory chip having a first side formed with no pads and a second side formed with pads is mounted on a mounting substrate. A control chip for controlling the nonvolatile memory chip is mounted on the nonvolatile memory chip. The control chip has a first pad row corresponding to the pads of the nonvolatile memory chip. The first pad row is mounted adjacent to the first side of the nonvolatile memory chip. The first pad row of the control chip and a first electrode row formed on the mounting substrate are connected via a first wire group. The pads of the nonvolatile memory chip and a second electrode row formed on the mounting substrate are connected via a second wire group. The first electrode row and the second electrode row are connected through wirings formed in the mounting substrate.
摘要翻译: 本发明是提供一种在确保可靠性和信号传输性能的同时提高尺寸减小和批量生产率的非易失性存储装置。 具有形成有焊盘的第一侧和形成有焊盘的第二侧的非易失性存储器芯片安装在安装基板上。 用于控制非易失存储器芯片的控制芯片安装在非易失性存储器芯片上。 控制芯片具有对应于非易失性存储器芯片的焊盘的第一焊盘行。 第一焊盘排安装在非易失性存储芯片的第一侧附近。 控制芯片的第一焊盘排和形成在安装基板上的第一电极列经由第一焊丝组连接。 形成在安装基板上的非易失性存储芯片的焊盘和第二电极列经由第二引线组连接。 第一电极列和第二电极列通过形成在安装基板中的布线连接。
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公开(公告)号:US07804176B2
公开(公告)日:2010-09-28
申请号:US11626286
申请日:2007-01-23
CPC分类号: H01L25/18 , G11C5/06 , H01L24/45 , H01L24/73 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48145 , H01L2224/48147 , H01L2224/48227 , H01L2224/49171 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06555 , H01L2225/06562 , H01L2225/06586 , H01L2924/01014 , H01L2924/01037 , H01L2924/01079 , H01L2924/10253 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要: This invention is to provide a nonvolatile memory device that enhances a size reduction and mass productivity while ensuring reliability and signal transmission performance. A nonvolatile memory chip having a first side formed with no pads and a second side formed with pads is mounted on a mounting substrate. A control chip for controlling the nonvolatile memory chip is mounted on the nonvolatile memory chip. The control chip has a first pad row corresponding to the pads of the nonvolatile memory chip. The first pad row is mounted adjacent to the first side of the nonvolatile memory chip. The first pad row of the control chip and a first electrode row formed on the mounting substrate are connected via a first wire group. The pads of the nonvolatile memory chip and a second electrode row formed on the mounting substrate are connected via a second wire group. The first electrode row and the second electrode row are connected through wirings formed in the mounting substrate.
摘要翻译: 本发明是提供一种在确保可靠性和信号传输性能的同时提高尺寸减小和批量生产率的非易失性存储装置。 具有形成有焊盘的第一侧和形成有焊盘的第二侧的非易失性存储器芯片安装在安装基板上。 用于控制非易失存储器芯片的控制芯片安装在非易失性存储器芯片上。 控制芯片具有对应于非易失性存储器芯片的焊盘的第一焊盘行。 第一焊盘排安装在非易失性存储芯片的第一侧附近。 控制芯片的第一焊盘排和形成在安装基板上的第一电极列经由第一焊丝组连接。 形成在安装基板上的非易失性存储芯片的焊盘和第二电极列经由第二引线组连接。 第一电极列和第二电极列通过形成在安装基板中的布线连接。
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公开(公告)号:US07332800B2
公开(公告)日:2008-02-19
申请号:US10860073
申请日:2004-06-04
申请人: Takashi Kikuchi , Ryosuke Kimoto , Hiroshi Kawakubo , Takashi Miwa , Chikako Imura , Takafumi Nishita , Hiroshi Koyama , Masanori Shibamoto , Masaru Kawakami
发明人: Takashi Kikuchi , Ryosuke Kimoto , Hiroshi Kawakubo , Takashi Miwa , Chikako Imura , Takafumi Nishita , Hiroshi Koyama , Masanori Shibamoto , Masaru Kawakami
IPC分类号: H01L23/02
CPC分类号: H01L23/3128 , H01L21/563 , H01L24/28 , H01L25/105 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/83102 , H01L2224/92125 , H01L2225/1023 , H01L2225/1058 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01019 , H01L2924/01033 , H01L2924/0105 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/1433 , H01L2924/15151 , H01L2924/15174 , H01L2924/15192 , H01L2924/15311 , H01L2924/1532 , H01L2924/3511 , H01L2924/00012 , H01L2924/00
摘要: For high density packaging of a semiconductor device, the semiconductor device has a multi-layer substrate, a first-stage chip connected electrically to the multi-layer substrate, other package substrates stacked in three stages on the multi-layer substrate and each connected to an underlying wiring substrate through solder balls, second-, third- and fourth-stage chips electrically connected respectively to the other package substrates, and solder balls provided on the bottom multi-layer substrate. The number of wiring layers in the bottom multi-layer substrate which has a logic chip is larger than that in the package substrates which have memory chips, whereby the semiconductor device can have a wiring layer not used for distribution of wires to the solder balls and wiring lines in the wiring layer can be used for the mounting of another semiconductor element or a passive component to attain high density packaging of the semiconductor device as a stacked type package.
摘要翻译: 对于半导体器件的高密度封装,半导体器件具有多层衬底,与多层衬底电连接的第一级芯片,在多层衬底上分层堆叠的其它封装衬底,并且每个衬底连接到 通过焊球,第二级,第三级和第四级芯片分别与其他封装衬底电连接的底层布线衬底以及设置在底部多层衬底上的焊球。 具有逻辑芯片的底部多层基板中的布线层数大于具有存储芯片的封装基板中的布线层的数量,由此半导体器件可以具有不用于将焊丝分布到焊球的布线层, 布线层中的布线可用于安装另一半导体元件或无源元件,以实现作为堆叠型封装的半导体器件的高密度封装。
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公开(公告)号:US20050040509A1
公开(公告)日:2005-02-24
申请号:US10860073
申请日:2004-06-04
申请人: Takashi Kikuchi , Ryosuke Kimoto , Hiroshi Kawakubo , Takashi Miwa , Chikako Imura , Takafumi Nishita , Hiroshi Koyama , Masanori Shibamoto , Masaru Kawakami
发明人: Takashi Kikuchi , Ryosuke Kimoto , Hiroshi Kawakubo , Takashi Miwa , Chikako Imura , Takafumi Nishita , Hiroshi Koyama , Masanori Shibamoto , Masaru Kawakami
CPC分类号: H01L23/3128 , H01L21/563 , H01L24/28 , H01L25/105 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/83102 , H01L2224/92125 , H01L2225/1023 , H01L2225/1058 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01019 , H01L2924/01033 , H01L2924/0105 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/1433 , H01L2924/15151 , H01L2924/15174 , H01L2924/15192 , H01L2924/15311 , H01L2924/1532 , H01L2924/3511 , H01L2924/00012 , H01L2924/00
摘要: For high density packaging of a semiconductor device, the semiconductor device has a multi-layer substrate, a first-stage chip connected electrically to the multi-layer substrate, other package substrates stacked in three stages on the multi-layer substrate and each connected to an underlying wiring substrate through solder balls, second-, third- and fourth-stage chips electrically connected respectively to the other package substrates, and solder balls provided on the bottom multi-layer substrate. The number of wiring layers in the bottom multi-layer substrate which has a logic chip is larger than that in the package substrates which have memory chips, whereby the semiconductor device can have a wiring layer not used for distribution of wires to the solder balls and wiring lines in the wiring layer can be used for the mounting of another semiconductor element or a passive component to attain high density packaging of the semiconductor device as a stacked type package.
摘要翻译: 对于半导体器件的高密度封装,半导体器件具有多层衬底,与多层衬底电连接的第一级芯片,在多层衬底上分层堆叠的其它封装衬底,并且每个衬底连接到 通过焊球,第二级,第三级和第四级芯片分别与其他封装衬底电连接的底层布线衬底以及设置在底部多层衬底上的焊球。 具有逻辑芯片的底部多层基板中的布线层数大于具有存储芯片的封装基板中的布线层的数量,由此半导体器件可以具有不用于将焊丝分布到焊球的布线层, 布线层中的布线可用于安装另一半导体元件或无源元件,以实现作为堆叠型封装的半导体器件的高密度封装。
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公开(公告)号:US06232653B1
公开(公告)日:2001-05-15
申请号:US09270500
申请日:1999-03-17
申请人: Naotaka Tanaka , Akihiro Yaguchi , Ryuji Kohno , Kiyomi Kojima , Takeshi Terasaki , Hideo Miura , Junichi Arita , Chikako Imura
发明人: Naotaka Tanaka , Akihiro Yaguchi , Ryuji Kohno , Kiyomi Kojima , Takeshi Terasaki , Hideo Miura , Junichi Arita , Chikako Imura
IPC分类号: H01L2348
CPC分类号: H01L23/4951 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/32014 , H01L2224/32245 , H01L2224/451 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/49175 , H01L2224/73215 , H01L2224/92147 , H01L2924/00014 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/14 , H01L2924/00 , H01L2924/00012 , H01L2924/00015 , H01L2224/05599
摘要: A TSOP type semiconductor device having a LOC structure employing a copper (alloy) type frame prevents resin cracks that occur in a reliability test such as a temperature cycle test. The TSOP type semiconductor device has narrower common inner leads where a resin crack would be likely to occur first, and has a thinner chip.
摘要翻译: 具有采用铜(合金)型框架的LOC结构的TSOP型半导体器件防止了在诸如温度循环测试的可靠性测试中发生的树脂裂纹。 TSOP型半导体器件具有较窄的公共内引线,其中首先可能发生树脂裂纹,并且具有更薄的芯片。
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公开(公告)号:US06610561B2
公开(公告)日:2003-08-26
申请号:US09849230
申请日:2001-05-07
申请人: Kunihiro Tsubosaki , Masachika Masuda , Akihiko Iwaya , Atsushi Nakamura , Chikako Imura , Toshihiro Shiotsuki
发明人: Kunihiro Tsubosaki , Masachika Masuda , Akihiko Iwaya , Atsushi Nakamura , Chikako Imura , Toshihiro Shiotsuki
IPC分类号: H01L2144
CPC分类号: H01L24/06 , H01L23/4951 , H01L23/49551 , H01L23/50 , H01L24/05 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/05599 , H01L2224/06136 , H01L2224/32014 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48599 , H01L2224/49171 , H01L2224/73215 , H01L2224/85399 , H01L2224/92147 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要: The present invention provides a thin, inexpensive, high-performance semiconductor device provided with busbar leads, power leads and signal leads. A portion of the power lead connected to the busbar lead is depressed toward a major surface of a semiconductor chip to form depressed portion, and the depressed portion is bonded to the major surface of the semiconductor chip by an adhesive layer. The signal lead and the busbar lead are spaced apart from the major surface of the semiconductor chip.
摘要翻译: 本发明提供一种薄型,廉价的高性能半导体器件,其具有母线引线,电源引线和信号引线。 连接到汇流条引线的电源引线的一部分朝向半导体芯片的主表面压下以形成凹陷部分,并且凹陷部分通过粘合剂层结合到半导体芯片的主表面。 信号引线和母线引线与半导体芯片的主表面间隔开。
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公开(公告)号:US6137159A
公开(公告)日:2000-10-24
申请号:US258300
申请日:1999-02-26
申请人: Kunihiro Tsubosaki , Masachika Masuda , Akihiko Iwaya , Atsushi Nakamura , Chikako Imura , Toshihiro Shiotsuki
发明人: Kunihiro Tsubosaki , Masachika Masuda , Akihiko Iwaya , Atsushi Nakamura , Chikako Imura , Toshihiro Shiotsuki
IPC分类号: H01L23/495 , H01L23/50
CPC分类号: H01L24/06 , H01L23/4951 , H01L23/49551 , H01L23/50 , H01L2224/04042 , H01L2224/05554 , H01L2224/06136 , H01L2224/32014 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/49171 , H01L2224/73215 , H01L2224/92147 , H01L24/05 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/181
摘要: The present invention provides a thin, inexpensive, high-performance semiconductor device provided with busbar leads, power leads and signal leads. A portion of the power lead connected to the busbar lead is depressed toward a major surface of a semiconductor chip to form a depressed portion, and the depressed portion is bonded to the major surface of the semiconductor chip by an adhesive layer. The signal lead and the busbar lead are spaced apart from the major surface of the semiconductor chip.
摘要翻译: 本发明提供一种薄型,廉价的高性能半导体器件,其具有母线引线,电源引线和信号引线。 连接到汇流条引线的电源引线的一部分朝向半导体芯片的主表面压下以形成凹陷部分,并且凹陷部分通过粘合剂层结合到半导体芯片的主表面。 信号引线和母线引线与半导体芯片的主表面间隔开。
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公开(公告)号:US06335227B1
公开(公告)日:2002-01-01
申请号:US09690451
申请日:2000-10-18
申请人: Kunihiro Tsubosaki , Masachika Masuda , Akihiko Iwaya , Atsushi Nakamura , Chikako Imura , Toshihiro Shiotsuki
发明人: Kunihiro Tsubosaki , Masachika Masuda , Akihiko Iwaya , Atsushi Nakamura , Chikako Imura , Toshihiro Shiotsuki
IPC分类号: H01L2144
CPC分类号: H01L24/06 , H01L23/4951 , H01L23/49551 , H01L23/50 , H01L24/05 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/04042 , H01L2224/05554 , H01L2224/06136 , H01L2224/32014 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/49171 , H01L2224/73215 , H01L2224/92147 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/181 , H01L2224/05599 , H01L2924/00 , H01L2924/00012 , H01L2224/85399
摘要: A method is provided for forming a thin, inexpensive, high-performance semiconductor device provided with busbar leads, power leads and signal leads. A portion of the power lead connected to the busbar lead is depressed toward a major surface of a semiconductor chip to form a depressed portion, and the depressed portion is bonded to the major surface of the semiconductor chip by an adhesive layer. The signal lead and the busbar lead are spaced apart from the major surface of the semiconductor chip.
摘要翻译: 提供了一种用于形成具有母线,电源引线和信号引线的薄型,便宜的高性能半导体器件的方法。 连接到汇流条引线的电源引线的一部分朝向半导体芯片的主表面压下以形成凹陷部分,并且凹陷部分通过粘合剂层结合到半导体芯片的主表面。 信号引线和母线引线与半导体芯片的主表面间隔开。
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