公开(公告)号：US20050040509A1

公开(公告)日：2005-02-24

申请号：US10860073

申请日：2004-06-04

申请人： Takashi Kikuchi ,  Ryosuke Kimoto ,  Hiroshi Kawakubo ,  Takashi Miwa ,  Chikako Imura ,  Takafumi Nishita ,  Hiroshi Koyama ,  Masanori Shibamoto ,  Masaru Kawakami

发明人： Takashi Kikuchi ,  Ryosuke Kimoto ,  Hiroshi Kawakubo ,  Takashi Miwa ,  Chikako Imura ,  Takafumi Nishita ,  Hiroshi Koyama ,  Masanori Shibamoto ,  Masaru Kawakami

IPC分类号： H01L23/12 ,  H01L21/56 ,  H01L23/31 ,  H01L25/10 ,  H05K1/00 ,  H01L21/48 ,  H01L23/02

CPC分类号： H01L23/3128 ,  H01L21/563 ,  H01L24/28 ,  H01L25/105 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15151 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00

摘要： For high density packaging of a semiconductor device, the semiconductor device has a multi-layer substrate, a first-stage chip connected electrically to the multi-layer substrate, other package substrates stacked in three stages on the multi-layer substrate and each connected to an underlying wiring substrate through solder balls, second-, third- and fourth-stage chips electrically connected respectively to the other package substrates, and solder balls provided on the bottom multi-layer substrate. The number of wiring layers in the bottom multi-layer substrate which has a logic chip is larger than that in the package substrates which have memory chips, whereby the semiconductor device can have a wiring layer not used for distribution of wires to the solder balls and wiring lines in the wiring layer can be used for the mounting of another semiconductor element or a passive component to attain high density packaging of the semiconductor device as a stacked type package.

摘要翻译： 对于半导体器件的高密度封装，半导体器件具有多层衬底，与多层衬底电连接的第一级芯片，在多层衬底上分层堆叠的其它封装衬底，并且每个衬底连接到 通过焊球，第二级，第三级和第四级芯片分别与其他封装衬底电连接的底层布线衬底以及设置在底部多层衬底上的焊球。 具有逻辑芯片的底部多层基板中的布线层数大于具有存储芯片的封装基板中的布线层的数量，由此半导体器件可以具有不用于将焊丝分布到焊球的布线层， 布线层中的布线可用于安装另一半导体元件或无源元件，以实现作为堆叠型封装的半导体器件的高密度封装。

公开(公告)号：US07332800B2

公开(公告)日：2008-02-19

申请号：US10860073

申请日：2004-06-04

申请人： Takashi Kikuchi ,  Ryosuke Kimoto ,  Hiroshi Kawakubo ,  Takashi Miwa ,  Chikako Imura ,  Takafumi Nishita ,  Hiroshi Koyama ,  Masanori Shibamoto ,  Masaru Kawakami

发明人： Takashi Kikuchi ,  Ryosuke Kimoto ,  Hiroshi Kawakubo ,  Takashi Miwa ,  Chikako Imura ,  Takafumi Nishita ,  Hiroshi Koyama ,  Masanori Shibamoto ,  Masaru Kawakami

IPC分类号： H01L23/02

CPC分类号： H01L23/3128 ,  H01L21/563 ,  H01L24/28 ,  H01L25/105 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15151 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00

摘要： For high density packaging of a semiconductor device, the semiconductor device has a multi-layer substrate, a first-stage chip connected electrically to the multi-layer substrate, other package substrates stacked in three stages on the multi-layer substrate and each connected to an underlying wiring substrate through solder balls, second-, third- and fourth-stage chips electrically connected respectively to the other package substrates, and solder balls provided on the bottom multi-layer substrate. The number of wiring layers in the bottom multi-layer substrate which has a logic chip is larger than that in the package substrates which have memory chips, whereby the semiconductor device can have a wiring layer not used for distribution of wires to the solder balls and wiring lines in the wiring layer can be used for the mounting of another semiconductor element or a passive component to attain high density packaging of the semiconductor device as a stacked type package.

摘要翻译： 对于半导体器件的高密度封装，半导体器件具有多层衬底，与多层衬底电连接的第一级芯片，在多层衬底上分层堆叠的其它封装衬底，并且每个衬底连接到 通过焊球，第二级，第三级和第四级芯片分别与其他封装衬底电连接的底层布线衬底以及设置在底部多层衬底上的焊球。 具有逻辑芯片的底部多层基板中的布线层数大于具有存储芯片的封装基板中的布线层的数量，由此半导体器件可以具有不用于将焊丝分布到焊球的布线层， 布线层中的布线可用于安装另一半导体元件或无源元件，以实现作为堆叠型封装的半导体器件的高密度封装。

公开(公告)号：US06060770A

公开(公告)日：2000-05-09

申请号：US7079

申请日：1998-01-14

申请人： Hisao Nakamura ,  Seiichi Ichihara ,  Ryosuke Kimoto ,  Hiroshi Kawakubo ,  Ryo Haruta ,  Hiroshi Koyama

发明人： Hisao Nakamura ,  Seiichi Ichihara ,  Ryosuke Kimoto ,  Hiroshi Kawakubo ,  Ryo Haruta ,  Hiroshi Koyama

IPC分类号： H01L23/28 ,  H01L21/56 ,  H01L21/60 ,  H01L23/495

CPC分类号： H01L24/50 ,  H01L23/49572 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181

摘要： The thickness of a tape carrier package having a semiconductor chip is made uniform where bonding pads are concentrated on one side of the semiconductor chip. The tape carrier package is such that dummy pads 6b are arranged on one side opposite to the side on which bonding pads (effective pins) 6a are arranged in the semiconductor chip. Dummy leads 5 are formed on an insulating tape 4. The semiconductor chip is supported with inner lead portions 5a connected to the corresponding bonding pads 6a and the inner lead portions 5a of the dummy leads 5 connected to the corresponding dummy pads 6b.

公开(公告)号：US06476467B2

公开(公告)日：2002-11-05

申请号：US09870824

申请日：2001-06-01

申请人： Hisao Nakamura ,  Seiichi Ichihara ,  Ryosuke Kimoto ,  Hiroshi Kawakubo ,  Ryo Haruta ,  Hiroshi Koyama

发明人： Hisao Nakamura ,  Seiichi Ichihara ,  Ryosuke Kimoto ,  Hiroshi Kawakubo ,  Ryo Haruta ,  Hiroshi Koyama

IPC分类号： H01L23495

CPC分类号： H01L24/50 ,  H01L23/49572 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05599

摘要： The thickness of a tape carrier package having a semiconductor chip is made uniform where bonding pads are concentrated on one side of the semiconductor chip. The tape carrier package is such that dummy pads 6b are arranged on one side opposite to the side on which bonding pads (effective pins) 6a are arranged in the semiconductor chip. Dummy leads 5 are formed on an insulating tape 4. The semiconductor chip is supported with inner lead portions 5a connected to the corresponding bonding pads 6a and the inner lead portions 5a of the dummy leads 5 connected to the corresponding dummy pads 6b.

摘要翻译： 具有半导体芯片的带状载体封装的厚度在焊盘集中在半导体芯片的一侧上时是均匀的。 磁带载体封装是这样的，即，虚拟焊盘6b布置在与半导体芯片中布置有焊盘（有效引脚）6a的一侧相对的一侧上。 虚拟引线5形成在绝缘带4上。半导体芯片由连接到相应的接合焊盘6a的内部引线部分5a和连接到相应的虚设焊盘6b的虚拟引线5的内部引线部分5a支撑。

公开(公告)号：US06278176B1

公开(公告)日：2001-08-21

申请号：US09545463

申请日：2000-04-07

申请人： Hisao Nakamura ,  Seiichi Ichihara ,  Ryosuke Kimoto ,  Hiroshi Kawakubo ,  Ryo Haruta ,  Hiroshi Koyama

发明人： Hisao Nakamura ,  Seiichi Ichihara ,  Ryosuke Kimoto ,  Hiroshi Kawakubo ,  Ryo Haruta ,  Hiroshi Koyama

IPC分类号： H01L2302

CPC分类号： H01L24/50 ,  H01L23/49572 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05599

摘要： The thickness of a tape carrier package having a semiconductor chip is made uniform where bonding pads are concentrated on one side of the semiconductor chip. The tape carrier package is such that dummy pads 6b are arranged on one side opposite to the side on which bonding pads (effective pins) 6a are arranged in the semiconductor chip. Dummy leads 5 are formed on an insulating tape 4. The semiconductor chip is supported with inner lead portions 5a connected to the corresponding bonding pads 6a and the inner lead portions 5a of the dummy leads 5 connected to the corresponding dummy pads 6b.

摘要翻译： 具有半导体芯片的带状载体封装的厚度在焊盘集中在半导体芯片的一侧上时是均匀的。 磁带载体封装是这样的，即，虚拟焊盘6b布置在与半导体芯片中布置有焊盘（有效引脚）6a的一侧相对的一侧上。 虚拟引线5形成在绝缘带4上。半导体芯片由连接到相应的接合焊盘6a的内部引线部分5a和连接到相应的虚设焊盘6b的虚拟引线5的内部引线部分5a支撑。

公开(公告)号：US07211892B2

公开(公告)日：2007-05-01

申请号：US11146044

申请日：2005-06-07

申请人： Shiro Yamashita ,  Yoichi Abe ,  Kenichi Yamamoto ,  Ryosuke Kimoto ,  Hiroshi Kawakubo

发明人： Shiro Yamashita ,  Yoichi Abe ,  Kenichi Yamamoto ,  Ryosuke Kimoto ,  Hiroshi Kawakubo

IPC分类号： H01L29/40

CPC分类号： H01L23/49816 ,  H01L24/11 ,  H01L24/12 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05644 ,  H01L2224/11822 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H05K3/067 ,  H05K3/244 ,  H05K3/3463 ,  H05K2201/0305 ,  H05K2203/0361 ,  H05K2203/1476 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： In order to inhibit the connection failure due to the degradation of the connection interface strength of the electrode pad and the warp thereof in the semiconductor device having an electrode pad, a metal layer formed on the electrode pad, and a metal bump formed on the metal layer, in the present invention, gold (Au) is contained in the metal layer, the metal bump is made of solder mainly made of Sn and designed to have an average height H of 100 μm or less per unit area in the electrode pad, and the concentration of Au of the metal layer dissolved in the solder is set to 1.3×10−3 (Vol %) or less. More preferably, the metal bump contains palladium (Pd), and the solder coating for forming the metal bump on the electrode pad is performed by using the dipping and the paste printing in combination.

摘要翻译： 为了抑制由于在具有电极焊盘的半导体器件中电极焊盘的连接界面强度的劣化及其翘曲导致的连接故障，形成在电极焊盘上的金属层和形成在金属上的金属凸块 在本发明中，在金属层中含有金（Au），金属凸块由主要由Sn制成的焊料制成，并且设计成在电极焊盘中的每单位面积的平均高度H为100mum以下， 并且溶解在焊料中的金属层的Au浓度设定为1.3×10 -3（Vol％）以下。 更优选地，金属凸块包含钯（Pd），并且通过组合使用浸渍和糊印来进行用于在电极焊盘上形成金属凸块的焊料涂层。

公开(公告)号：US20060151877A1

公开(公告)日：2006-07-13

申请号：US11146044

申请日：2005-06-07

申请人： Shiro Yamashita ,  Yoichi Abe ,  Kenichi Yamamoto ,  Ryosuke Kimoto ,  Hiroshi Kawakubo

发明人： Shiro Yamashita ,  Yoichi Abe ,  Kenichi Yamamoto ,  Ryosuke Kimoto ,  Hiroshi Kawakubo

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L23/49816 ,  H01L24/11 ,  H01L24/12 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05644 ,  H01L2224/11822 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H05K3/067 ,  H05K3/244 ,  H05K3/3463 ,  H05K2201/0305 ,  H05K2203/0361 ,  H05K2203/1476 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： In order to inhibit the connection failure due to the degradation of the connection interface strength of the electrode pad and the warp thereof in the semiconductor device having an electrode pad, a metal layer formed on the electrode pad, and a metal bump formed on the metal layer, in the present invention, gold (Au) is contained in the metal layer, the metal bump is made of solder mainly made of Sn and designed to have an average height H of 100 μm or less per unit area in the electrode pad, and the concentration of Au of the metal layer dissolved in the solder is set to 1.3×10−3 (Vol %) or less. More preferably, the metal bump contains palladium (Pd), and the solder coating for forming the metal bump on the electrode pad is performed by using the dipping and the paste printing in combination.

摘要翻译： 为了抑制由于在具有电极焊盘的半导体器件中电极焊盘的连接界面强度的劣化及其翘曲导致的连接故障，形成在电极焊盘上的金属层和形成在金属上的金属凸块 在本发明中，在金属层中含有金（Au），金属凸块由主要由Sn制成的焊料制成，并且设计成在电极焊盘中的每单位面积的平均高度H为100mum以下， 并且溶解在焊料中的金属层的Au浓度设定为1.3×10 -3（Vol％）以下。 更优选地，金属凸块包含钯（Pd），并且通过组合使用浸渍和糊印来进行用于在电极焊盘上形成金属凸块的焊料涂层。

公开(公告)号：US20070013083A1

公开(公告)日：2007-01-18

申请号：US11482764

申请日：2006-07-10

申请人： Takashi Kikuchi ,  Koichi Kanemoto ,  Michiaki Sugiyama ,  Hiroshi Kawakubo

发明人： Takashi Kikuchi ,  Koichi Kanemoto ,  Michiaki Sugiyama ,  Hiroshi Kawakubo

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H05K1/111 ,  H01L21/4853 ,  H01L23/49816 ,  H01L23/5386 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/3452 ,  H05K3/3484 ,  H05K2201/09381 ,  H05K2201/09418 ,  H05K2201/0989 ,  H05K2201/099 ,  H05K2201/10734 ,  H05K2203/043 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

摘要： Improvement in the mountability of a semiconductor device is aimed at. By preparing a package substrate which has a plurality of lands of NSMD structure, and the taking-out wiring and dummy wiring which were connected to each of the lands, and have been arranged mutually in the location of 180° symmetry, and printing solder by a printing method to the lands after the package assembly, the variation in the height of the solder coat between lands can be reduced, and improvement in the mountability of LGA (semiconductor device) is aimed at.

摘要翻译： 目的在于提高半导体器件的安装性能。 通过制备具有多个NSMD结构的焊盘的封装基板，以及连接到每个焊盘并被相互放置在180度对称位置的引出布线和虚拟布线，并且通过 在封装组件之后的印刷方法到达焊盘的焊盘的高度的变化可以减小，并且针对LGA（半导体器件）的安装性能的提高。

公开(公告)号：US06214639B1

公开(公告)日：2001-04-10

申请号：US09365820

申请日：1999-08-03

申请人： Masaomi Emori ,  Mitsuji Nunokawa ,  Kenichi Hiratsuka ,  Masanori Ishii ,  Hiroshi Kawakubo

发明人： Masaomi Emori ,  Mitsuji Nunokawa ,  Kenichi Hiratsuka ,  Masanori Ishii ,  Hiroshi Kawakubo

IPC分类号： H01L2148

CPC分类号： H01L21/6835 ,  H01L21/3043 ,  H01L21/6836 ,  H01L21/78 ,  H01L2221/68327 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2221/68377

摘要： A method of producing a semiconductor device including a step of forming separation grooves in scribing regions defined at boundary portions between a plurality of semiconductor-device forming portions formed on a top surface of a semiconductor substrate; a step of defining portions of the scribing regions in the semiconductor substrate as substrate connecting portions; and a step of cutting off the substrate connecting portions along the separation grooves, to thereby separate the plurality of semiconductor-device forming portions into chips. These production steps contribute to a higher working efficiency in a later assembling process and to improved mass-production.

摘要翻译： 一种制造半导体器件的方法，包括在形成在半导体衬底的顶表面上的多个半导体器件形成部分之间的边界部分限定的划线区域中形成分隔槽的步骤; 将所述半导体衬底中的所述划线区域的部分定义为衬底连接部分的步骤; 以及切断沿着分隔槽的基板连接部分的步骤，从而将多个半导体器件形成部分分离成芯片。 这些生产步骤有助于在后来的组装过程中提高工作效率并改善批量生产。

公开(公告)号：US08541298B2

公开(公告)日：2013-09-24

申请号：US13185002

申请日：2011-07-18

申请人： Hiroshi Kawakubo

发明人： Hiroshi Kawakubo

IPC分类号： H01L21/44

CPC分类号： H01L21/76898 ,  H01L21/30621 ,  H01L21/3065 ,  H01L29/1608

摘要： A method for fabricating a semiconductor device having a GaN-based semiconductor layer on a first surface of a substrate made of SiC, a pad being provided on the GaN-based layer, includes: forming a first via hole in the substrate by etching, with fluorine based gas, from a second surface of the substrate opposite to the first surface, the etching being carried out with the GaN-based layer being used as an etch stopper; and forming a second via hole in the GaN-based semiconductor layer, with chlorine based gas, from a bottom surface of the first via hole, the etching being carried out with the pad being used as an etching stopper, the chlorine based gas being an etchant different from the fluorine based gas.

摘要翻译： 一种制造半导体器件的方法，所述半导体器件在由SiC制成的衬底的第一表面上具有GaN基半导体层，所述衬底设置在所述GaN基层上，包括：通过蚀刻在所述衬底中形成第一通孔， 氟基气体，从基板的与第一表面相对的第二表面，蚀刻是用GaN基层作为蚀刻停止层进行的; 并且在所述GaN基半导体层中形成第二通孔，所述第二通孔与所述第一通孔的底表面形成有氯基气体，所述蚀刻用所述焊盘作为蚀刻停止层进行，所述氯基气体为 不同于氟基气体的蚀刻剂。