摘要:
A paging receiver includes a nonvolatile memory which is readable for controlling the operation of the paging device and is capable of being partitioned into a plurality of regions. A protect means is also included for allowing modification to a selected region of the nonvolatile memory in response to an unlock signal. In a first embodiment, the unlock signal is externally applied to the paging receiver. In a second embodiment, the unlock signal is generated when a predetermined coded signal stored in the paging receiver matches a received coded signal. In a third embodiment, the protect means further includes a switch means to permit the selected region of memory to be modified while preventing other regions of memory to be modified.
摘要:
A timer which can be used to provide interrupt signals at predetermined but variable periods for multi-tasking microcomputers or serial data acquisition in pagers comprises a plurality of modulo counters. Each modulo counter has selectable clock inputs and has an output coupled via switches to a NOR gate and to the other modulo counters. Programmable configuring means control the switching means to configure the counters so as to produce desired outputs at the logic gate. The configuring means can also reset the modulus of the modulo counters to any desired value. Thus, the timer produces variable interrupt signals with little or no overhead processor time.
摘要:
A Schmitt trigger has a first inverter, a second inverter, a bias means, and a transistor. The inverter has an input and an output. The second inverter has an input coupled to the output of the first inverter and has an output. The bias means provides a first bias voltage on a first output terminal. A magnitude of the bias voltage is selectable by a first input signal. The transistor has a first current electrode coupled to a first power supply terminal, a control electrode coupled to the output of the second inverter, a second current electrode coupled to the output of the first inverter, and a body coupled to the first output terminal. Selectability of the magnitude of the bias voltage provides selectability of the hysteresis of the Schmitt trigger.
摘要:
A dual bandwidth crystal controlled oscillator is described having a first transconductance amplifier providing sufficient gain to maintain oscillation with an oscillator crystal at a minimum current drain. A second transconductance amplifier is provided which can be selectively coupled to the first transconductance amplifier, thereby augmenting the gain of the first transconductance amplifier to provide the capability for rapid oscillator start-up following battery saver operation. The dual bandwidth crystal controlled oscillator can be utilized in conventional oscillator and frequency synthesizer applications.
摘要:
First and second unused bits of a multi-bit mapped register are utilized to control a desired function. Each of the bits are capable of assuming first and second stable states. The control function is enabled when the first bit is in the first state and the second bit is in a second state. The function is disabled when the first bit is in the second state and the second bit is in the first state. The function remains unaltered when the first and second bits are each in the same state.
摘要:
A phase locked loop (PLL) is provided having a filter with a programmable wide and narrow bandwith. When PLL circuit operation is initiated or when the operational frequency of the PLL is changed by a substantial amount, a phase detector functions to force the filter in a wide bandwith mode to allow fast circuit operation in the transient mode. After the PLL output has settled close to a predetermined frequency, the number of times the output frequency varies above and below the predetermined frequency before reaching a locked state is detected and counted. After the output frequency has varied above and below the predetermined frequency a predetermined number of times, the filter is automatically switched to a low bandwith mode to allow the PLL to operate in a stable manner.
摘要:
A voltage regulator for a memory that regulates a voltage provided to the memory cells based on a measured leakage current from a second set of memory cells. In one embodiment, based on the measured leakage current, the voltage to the cells is raised or lowered to control the amount of leakage current from the cells.
摘要:
Electromagnetic shielding for an integrated circuit packaged device. The method includes forming shielding structures by forming openings in an encapsulated structure. The openings are filled with conductive material that surrounds at least one die. The encapsulated structure may include a plurality of integrated circuit die. A layered redistribution structure is formed on one side of the encapsulated structure.
摘要:
Forming a packaged device having a semiconductor device having a first major surface and a second major surface includes forming an encapsulating layer over the second major surface of the semiconductor device and around sides of the semiconductor device and leaving the first major surface of the first semiconductor device exposed. A first insulating layer is formed over the first major surface. A plurality of vias are formed in the first insulating layer. A plurality of contacts are formed to the semiconductor device through the first plurality of vias, wherein each of the plurality of contacts has a surface above the first insulating layer. A supporting layer is formed over the first insulating layer leaving an opening over the first plurality of contacts wherein the opening has a sidewall surrounding the plurality of contacts.
摘要:
Apparatus and methods are described for a background microcontroller debugger. A method to debug a microcontroller includes sending a three level signal from a debug module, receiving the three level signal at a single pin on an MCU, sending a second three level signal from the single pin on the MCU, and receiving the second three level signal at the debug module. An apparatus to debug a microcontroller includes a tri-statable pad driver to transmit a three level signal, a reference voltage divider coupled to the tri-statable pad diver, a plurality of voltage comparators to receive the three level signal, a resistive voltage divider to maintain thresholds for the plurality of voltage comparators, and a plurality of logic elements coupled to the plurality of voltage comparators to receive the three level signal.