Paging receiver having selectively protected regions of memory
    1.
    发明授权
    Paging receiver having selectively protected regions of memory 失效
    寻呼接收机具有有选择地保护的存储区域

    公开(公告)号:US4839628A

    公开(公告)日:1989-06-13

    申请号:US141802

    申请日:1988-01-11

    IPC分类号: G08B3/10 H04W8/24 H04W88/02

    摘要: A paging receiver includes a nonvolatile memory which is readable for controlling the operation of the paging device and is capable of being partitioned into a plurality of regions. A protect means is also included for allowing modification to a selected region of the nonvolatile memory in response to an unlock signal. In a first embodiment, the unlock signal is externally applied to the paging receiver. In a second embodiment, the unlock signal is generated when a predetermined coded signal stored in the paging receiver matches a received coded signal. In a third embodiment, the protect means further includes a switch means to permit the selected region of memory to be modified while preventing other regions of memory to be modified.

    摘要翻译: 寻呼接收机包括非易失性存储器,该非易失性存储器可读取以用于控制寻呼装置的操作并且能够被划分成多个区域。 还包括用于响应于解锁信号修改非易失性存储器的选定区域的保护装置。 在第一实施例中,解锁信号被外部施加到寻呼接收机。 在第二实施例中,当存储在寻呼接收机中的预定编码信号与接收到的编码信号相匹配时,产生解锁信号。 在第三实施例中,保护装置还包括开关装置,以允许修改所选择的存储器区域,同时防止其他存储器区域被修改。

    Timer architecture for multi-task computers and for serial data decoding
    2.
    发明授权
    Timer architecture for multi-task computers and for serial data decoding 失效
    用于多任务计算机和串行数据解码的定时器架构

    公开(公告)号:US4879733A

    公开(公告)日:1989-11-07

    申请号:US149323

    申请日:1988-01-28

    IPC分类号: G06F1/14

    CPC分类号: G06F1/14

    摘要: A timer which can be used to provide interrupt signals at predetermined but variable periods for multi-tasking microcomputers or serial data acquisition in pagers comprises a plurality of modulo counters. Each modulo counter has selectable clock inputs and has an output coupled via switches to a NOR gate and to the other modulo counters. Programmable configuring means control the switching means to configure the counters so as to produce desired outputs at the logic gate. The configuring means can also reset the modulus of the modulo counters to any desired value. Thus, the timer produces variable interrupt signals with little or no overhead processor time.

    摘要翻译: 可以用于为预定但可变周期提供用于多任务微型计算机或寻呼机中的串行数据采集的中断信号的定时器包括多个模计数器。 每个模计数器具有可选择的时钟输入,并具有通过开关耦合到或非门和另一个模计数器的输出。 可编程配置意味着控制开关装置配置计数器,以便在逻辑门产生所需的输出。 配置装置还可以将模计数器的模数重置为任何期望的值。 因此,定时器产生可变中断信号,具有很少或没有开销的处理器时间。

    SCHMITT TRIGGER HAVING VARIABLE HYSTERESIS AND METHOD THEREFOR
    3.
    发明申请
    SCHMITT TRIGGER HAVING VARIABLE HYSTERESIS AND METHOD THEREFOR 审中-公开
    具有可变HYSTERESIS及其方法的SCHMITT触发器

    公开(公告)号:US20090237135A1

    公开(公告)日:2009-09-24

    申请号:US12053005

    申请日:2008-03-21

    IPC分类号: H03K3/00

    CPC分类号: H03K3/3565 H03K2217/0018

    摘要: A Schmitt trigger has a first inverter, a second inverter, a bias means, and a transistor. The inverter has an input and an output. The second inverter has an input coupled to the output of the first inverter and has an output. The bias means provides a first bias voltage on a first output terminal. A magnitude of the bias voltage is selectable by a first input signal. The transistor has a first current electrode coupled to a first power supply terminal, a control electrode coupled to the output of the second inverter, a second current electrode coupled to the output of the first inverter, and a body coupled to the first output terminal. Selectability of the magnitude of the bias voltage provides selectability of the hysteresis of the Schmitt trigger.

    摘要翻译: 施密特触发器具有第一反相器,第二反相器,偏置装置和晶体管。 变频器有一个输入和一个输出。 第二反相器具有耦合到第一反相器的输出并具有输出的输入。 偏置装置在第一输出端上提供第一偏置电压。 偏置电压的大小由第一输入信号选择。 晶体管具有耦合到第一电源端子的第一电流电极,耦合到第二反相器的输出的控制电极,耦合到第一反相器的输出的第二电流电极和耦合到第一输出端子的主体。 偏置电压大小的可选性提供了施密特触发器的滞后的可选性。

    Multiple bandwidth crystal controlled oscillator
    4.
    发明授权
    Multiple bandwidth crystal controlled oscillator 失效
    多带宽晶体振荡器

    公开(公告)号:US4896122A

    公开(公告)日:1990-01-23

    申请号:US380047

    申请日:1989-07-14

    IPC分类号: H03B5/32

    摘要: A dual bandwidth crystal controlled oscillator is described having a first transconductance amplifier providing sufficient gain to maintain oscillation with an oscillator crystal at a minimum current drain. A second transconductance amplifier is provided which can be selectively coupled to the first transconductance amplifier, thereby augmenting the gain of the first transconductance amplifier to provide the capability for rapid oscillator start-up following battery saver operation. The dual bandwidth crystal controlled oscillator can be utilized in conventional oscillator and frequency synthesizer applications.

    摘要翻译: 描述了双带宽晶体控制振荡器,其具有提供足够增益的第一跨导放大器,以使振荡器晶体保持最小电流消耗的振荡。 提供第二跨导放大器,其可以选择性地耦合到第一跨导放大器,从而增加第一跨导放大器的增益,以提供在节电器操作之后的快速振荡器启动的能力。 双频带晶振控制振荡器可用于常规振荡器和频率合成器应用。

    Hidden control bits in a control register
    5.
    发明授权
    Hidden control bits in a control register 失效
    控制寄存器中的隐藏控制位

    公开(公告)号:US4771405A

    公开(公告)日:1988-09-13

    申请号:US851993

    申请日:1986-04-14

    IPC分类号: G11C7/22 G11C8/18 G11C7/00

    CPC分类号: G11C8/18 G11C7/22

    摘要: First and second unused bits of a multi-bit mapped register are utilized to control a desired function. Each of the bits are capable of assuming first and second stable states. The control function is enabled when the first bit is in the first state and the second bit is in a second state. The function is disabled when the first bit is in the second state and the second bit is in the first state. The function remains unaltered when the first and second bits are each in the same state.

    摘要翻译: 利用多位映射寄存器的第一和第二未使用的位来控制所需的功能。 每个位都能够采取第一和第二稳定状态。 当第一位处于第一状态并且第二位处于第二状态时,控制功能被使能。 当第一个位处于第二个状态,第二个位处于第一个状态时,该功能被禁止。 当第一和第二位各自处于相同状态时,该功能保持不变。

    Phase locked loop having a filter with controlled variable bandwidth
    6.
    发明授权
    Phase locked loop having a filter with controlled variable bandwidth 失效
    锁相环具有带有可变带宽的滤波器

    公开(公告)号:US4771249A

    公开(公告)日:1988-09-13

    申请号:US53653

    申请日:1987-05-26

    摘要: A phase locked loop (PLL) is provided having a filter with a programmable wide and narrow bandwith. When PLL circuit operation is initiated or when the operational frequency of the PLL is changed by a substantial amount, a phase detector functions to force the filter in a wide bandwith mode to allow fast circuit operation in the transient mode. After the PLL output has settled close to a predetermined frequency, the number of times the output frequency varies above and below the predetermined frequency before reaching a locked state is detected and counted. After the output frequency has varied above and below the predetermined frequency a predetermined number of times, the filter is automatically switched to a low bandwith mode to allow the PLL to operate in a stable manner.

    摘要翻译: 提供了具有可编程宽带窄带滤波器的锁相环(PLL)。 当PLL电路工作开始时,或当PLL的工作频率变化很大时,相位检测器起到强制滤波器处于宽频带模式以允许瞬态模式下的快速电路运行的作用。 在PLL输出稳定在预定频率附近之后,检测并计数在达到锁定状态之前输出频率在预定频率之上变化高于和低于该频率的次数。 在输出频率高于和低于预定频率预定次数之后,滤波器自动切换到低频带模式以允许PLL以稳定的方式操作。

    Asynchronous debug interface
    10.
    发明授权
    Asynchronous debug interface 有权
    异步调试接口

    公开(公告)号:US07089467B2

    公开(公告)日:2006-08-08

    申请号:US10225058

    申请日:2002-08-21

    申请人: Kenneth R. Burch

    发明人: Kenneth R. Burch

    IPC分类号: G01R31/28

    CPC分类号: H04L1/22

    摘要: Apparatus and methods are described for a background microcontroller debugger. A method to debug a microcontroller includes sending a three level signal from a debug module, receiving the three level signal at a single pin on an MCU, sending a second three level signal from the single pin on the MCU, and receiving the second three level signal at the debug module. An apparatus to debug a microcontroller includes a tri-statable pad driver to transmit a three level signal, a reference voltage divider coupled to the tri-statable pad diver, a plurality of voltage comparators to receive the three level signal, a resistive voltage divider to maintain thresholds for the plurality of voltage comparators, and a plurality of logic elements coupled to the plurality of voltage comparators to receive the three level signal.

    摘要翻译: 描述了背景微控制器调试器的装置和方法。 调试微控制器的方法包括从调试模块发送三电平信号,在MCU的单个引脚上接收三电平信号,从MCU上的单个引脚发送第二个三电平信号,并接收第二个三电平 信号在调试模块。 用于调试微控制器的装置包括用于传输三电平信号的三态焊盘驱动器,耦合到三态电位垫潜水员的参考分压器,用于接收三电平信号的多个电压比较器,电阻分压器 维持多个电压比较器的阈值,以及耦合到多个电压比较器的多个逻辑元件以接收三电平信号。