公开(公告)号：US5907187A

公开(公告)日：1999-05-25

申请号：US502587

申请日：1995-07-14

申请人： Kaoru Koiwa ,  Koji Yamakawa ,  Kiyoshi Iyogi ,  Takaaki Yasumoto ,  Nobuo Iwase

发明人： Kaoru Koiwa ,  Koji Yamakawa ,  Kiyoshi Iyogi ,  Takaaki Yasumoto ,  Nobuo Iwase

IPC分类号： H01L23/498 ,  H05K3/34 ,  H01L23/48 ,  H01L23/06 ,  H01L23/52 ,  H01L29/40

CPC分类号： H05K3/3436 ,  H01L23/49816 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K2201/094 ,  H05K2201/10992 ,  H05K2203/041 ,  H05K3/3463 ,  H05K3/3484 ,  Y02P70/613

摘要： In such electronic components as semiconductor packages and semiconductor chips which are possessed of groups of connecting bumps as input and output terminals, the groups of connecting bumps comprise not less than two kinds of connecting bumps different in melting point or not less than two kinds of connecting bumps different in mechanical strength. The groups of connecting bumps comprise connecting bumps made of high temperature solder or connecting bumps made of a high strength In type solder in the part of formation thereof. The connecting bumps made of high temperature solder are not directly affected by the influence of displacement because they retain the shape of a ball even after the step of connection such as solder reflow. The connecting bumps made of In type solder form connecting parts of high strength. These groups of connecting bumps contribute to exalt the reliability of the connecting parts without decreasing the number of input and output terminals.

摘要翻译： 在具有作为输入和输出端子的连接凸块组的半导体封装和半导体芯片的这种电子部件中，连接凸块组包括不少于两种不同熔点的连接凸块或不少于两种连接 不同的机械强度凸起。 连接凸块的组包括在其形成部分中由高温焊料或由高强度In型焊料制成的连接凸块形成的连接凸块。 由高温焊料制成的连接凸块不受位移影响的直接影响，因为即使在诸如焊料回流的连接步骤之后，它们保持了球的形状。 由In型焊料形成的连接凸块形成高强度的连接部件。 这些连接凸块组有助于提高连接部件的可靠性，而不会减少输入和输出端子的数量。

公开(公告)号：US5326623A

公开(公告)日：1994-07-05

申请号：US10298

申请日：1993-01-28

申请人： Koji Yamakawa ,  Kaoru Koiwa ,  Takaaki Yasumoto ,  Kiyoshi Iyogi ,  Nobuo Iwase

发明人： Koji Yamakawa ,  Kaoru Koiwa ,  Takaaki Yasumoto ,  Kiyoshi Iyogi ,  Nobuo Iwase

IPC分类号： C04B37/02 ,  H01L23/12 ,  H01L23/15 ,  H01L23/498 ,  H01L23/538 ,  H05K1/09 ,  H05K3/24 ,  B32B9/00

CPC分类号： H01L23/538 ,  H01L23/49866 ,  H01L2924/0002 ,  H01L2924/09701 ,  Y10S428/901 ,  Y10T428/24917 ,  Y10T428/24926

摘要： A circuit board including a circuit pattern adhered firmly to a ceramic substrate and capable of eliminating an increase in resistivity due to an influence of an external environment, particularly, a thermal influence is disclosed. The circuit board comprises a ceramic substrate, and a circuit pattern formed on the substrate and having a multilayered structure in which a bonding layer comprising Ti and at least one element selected from the group consisting of N and O, a conductor layer consisting essentially of Cu, and a protective layer comprising Ti and at least one element selected from the group consisting of N and O are stacked in the order named.

摘要翻译： 公开了一种电路板，其包括牢固地粘附在陶瓷基板上的电路图形，能够消除由外部环境的影响引起的电阻率的增加，特别是热影响。 电路板包括陶瓷基板和形成在基板上并具有多层结构的电路图案，其中包含Ti和至少一种选自N和O的元素的接合层，基本上由Cu组成的导体层 ，并且以所述顺序堆叠包含Ti和从N和O组成的组中选择的至少一种元素的保护层。

公开(公告)号：US5622769A

公开(公告)日：1997-04-22

申请号：US194495

申请日：1994-02-10

申请人： Shoji Kozuka ,  Masaru Hayashi ,  Katsuyoshi Oh-Ishi ,  Takaaki Yasumoto ,  Nobuo Iwase ,  Hiroshi Endo ,  Koji Yamakawa ,  Kaoru Koiwa ,  Kiyoshi Iyogi

发明人： Shoji Kozuka ,  Masaru Hayashi ,  Katsuyoshi Oh-Ishi ,  Takaaki Yasumoto ,  Nobuo Iwase ,  Hiroshi Endo ,  Koji Yamakawa ,  Kaoru Koiwa ,  Kiyoshi Iyogi

IPC分类号： H01L23/15 ,  H05K1/03 ,  H05K3/38 ,  B32B3/00

CPC分类号： H05K3/38 ,  H01L23/15 ,  H01L2924/0002 ,  H05K1/0306 ,  Y10S428/901 ,  Y10T428/24917

摘要： According to this invention, there is disclosed a thermal conductivity substrate which includes an aluminum nitride sintered body and a coating layer formed on the body of aluminum phosphate and having a surface roughness of 1 .mu.m or less, and which has excellent humidity resistance and chemical resistance.

摘要翻译： 根据本发明，公开了一种导热性基材，其包括氮化铝烧结体和形成在磷酸铝体上的表面粗糙度为1μm以下并且具有优异的耐湿性和化学性质的涂层 抵抗性。

公开(公告)号：US5412160A

公开(公告)日：1995-05-02

申请号：US212869

申请日：1994-03-15

申请人： Takaaki Yasumoto ,  Nobuo Iwase ,  Kaoru Koiwa ,  Koji Yamakawa ,  Kiyoshi Iyogi

发明人： Takaaki Yasumoto ,  Nobuo Iwase ,  Kaoru Koiwa ,  Koji Yamakawa ,  Kiyoshi Iyogi

IPC分类号： H01L23/373 ,  H05K1/02 ,  H05K1/00

CPC分类号： H01L23/3731 ,  H01L23/3732 ,  H01L23/3733 ,  H05K1/024 ,  H05K3/4605 ,  H05K3/467 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K2201/0116 ,  H05K2201/0179

摘要： A circuit board comprising a substrate, at least one dielectric film formed on the substrate and made of at least one selected from the group consisting of AlN, BN, diamond, diamond-like carbon, BeO and SiC, the dielectric film having pores of a porosity of 5 to 95% by volume, and at least one wiring metal film formed on the dielectric film.

摘要翻译： 一种电路板，包括基板，至少一个电介质膜，形成在基板上，由选自AlN，BN，金刚石，类金刚石碳，BeO和SiC中的至少一种制成，电介质膜具有孔 5〜95体积％的孔隙率和形成在电介质膜上的至少一个布线金属膜。

公开(公告)号：US4855251A

公开(公告)日：1989-08-08

申请号：US267707

申请日：1988-11-03

申请人： Kiyoshi Iyogi ,  Koji Yamakawa ,  Nobuo Iwase

发明人： Kiyoshi Iyogi ,  Koji Yamakawa ,  Nobuo Iwase

IPC分类号： H01L21/60 ,  H01L23/485

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L2224/11003 ,  H01L2224/111 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2924/0001 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  Y10T29/49121

摘要： According to the present invention, a method is provided of manufacturing electronic parts, comprising a first step of forming on the surface of a substrate a bump wherein the metal particles of that portion of the bump which contacts the surface of the substrate have a larger diameter than the metal particles of that portion of the bump which does not contact the surface of the substrate, a second step of transferring the bump to an electrode lead, and a third step of connecting an electrode lead to a predetermined electrode section of the semiconductor chip, by means of the transferred bump. The method of the present invention ensures that the bump does not fall off during the electroplating and washing steps, and ensures a high-strength bond between the transferred bump and the electrode section of a semiconductor chip.

摘要翻译： 根据本发明，提供了一种制造电子部件的方法，该方法包括：在基板的表面上形成凸块的第一步骤，其中与基板表面接触的该凸块部分的金属颗粒具有较大的直径 比不与基板表面接触的部分凸块的金属颗粒，将凸点转移到电极引线的第二步骤，以及将电极引线连接到半导体芯片的预定电极部分的第三步骤 ，通过转移的凸块。 本发明的方法确保了在电镀和洗涤步骤期间凸起不会脱落，并确保了转印凸块与半导体芯片的电极部分之间的高强度结合。

公开(公告)号：US5041700A

公开(公告)日：1991-08-20

申请号：US588928

申请日：1990-09-27

申请人： Kiyoshi Iyogi ,  Takaaki Yasumoto ,  Toshirou Yanazawa ,  Nobuo Iwase

发明人： Kiyoshi Iyogi ,  Takaaki Yasumoto ,  Toshirou Yanazawa ,  Nobuo Iwase

IPC分类号： C04B37/02 ,  C04B41/52 ,  C04B41/89 ,  H01L23/15 ,  H01L23/498 ,  H05K1/03 ,  H05K3/38

CPC分类号： C04B41/009 ,  C04B41/52 ,  C04B41/89 ,  H01L23/15 ,  H01L23/49866 ,  H01L2924/0002 ,  H01L2924/15312 ,  H05K1/0306 ,  H05K3/38

摘要： A circuit board includes an aluminum nitride substrate, and a circuit pattern formed on the substrate and having a multilayered structure in which a metal oxynitride layer represented by formula Al.sub.u Ml.sub.v M2.sub.x O.sub.y N.sub.z (wherein M1 represents a metal selected from the group consisting of Ti, Cr, Ta, and Zr, M2 represents a metal selected from the group consisting of Ni, Pt, Pd, W, Nb, and Mo, u represents 3 to 50 atm %, v represents 3 to 78 atm %, x represents 0 to 50 atm %, y represents 0.005 to 25 atm %, and z represents 5 to 70 atm %), a bonding layer consisting essentially of a metal represented by M1, a barrier layer consisting essentially of a metal represented by M2, and a conductor layer consisting essentially of Au are stacked in the order named.

摘要翻译： 电路板包括氮化铝衬底和形成在衬底上并具有多层结构的电路图案，其中由式AluMlvM2xOyNz表示的金属氧氮化物层（其中M1表示选自Ti，Cr，Ta， Zr，M2表示选自Ni，Pt，Pd，W，Nb和Mo的金属，u表示3〜50atm％，v表示3〜78atm％，x表示0〜50atm％ y表示0.005〜25atm％，z表示5〜70atm％），基本上由M1表示的金属构成的接合层，基本上由M2表示的金属构成的阻挡层和基本上由Au构成的导体层 按照命名的顺序堆叠。

公开(公告)号：US4659611A

公开(公告)日：1987-04-21

申请号：US706280

申请日：1985-02-27

申请人： Nobuo Iwase ,  Kazuo Anzai ,  Kazuo Shinozaki ,  Akihiko Tsuge ,  Kazutaka Saitoh ,  Kiyoshi Iyogi ,  Noboru Sato ,  Mitsuo Kasori

发明人： Nobuo Iwase ,  Kazuo Anzai ,  Kazuo Shinozaki ,  Akihiko Tsuge ,  Kazutaka Saitoh ,  Kiyoshi Iyogi ,  Noboru Sato ,  Mitsuo Kasori

IPC分类号： C04B41/51 ,  C04B41/52 ,  C04B41/88 ,  C04B41/89 ,  H01L23/15 ,  H01L23/373 ,  H05K1/03 ,  C04B35/52 ,  B32B5/16 ,  B32B15/04 ,  C04B35/58

CPC分类号： C04B41/009 ,  C04B41/5111 ,  C04B41/52 ,  C04B41/88 ,  C04B41/89 ,  H01L23/15 ,  H01L23/3731 ,  C04B2111/00844 ,  H01L2924/0002 ,  H05K1/0306 ,  Y10S428/901 ,  Y10T428/24917 ,  Y10T428/24926

摘要： A high thermal conductivity circuit substrate is provided comprising a sintered aluminum nitride ceramic substrate consisting essentially of one member selected from the group of yttrium, the rare earth metals and the alkali earth metals and an electrically conductive thick film paste for a conductive layer formed on the substrate.

摘要翻译： 提供了一种高导热性电路基板，其包括基本上由选自钇，稀土金属和碱土金属的一种元素组成的烧结氮化铝陶瓷基板，以及形成在导电层上的导电厚膜糊 基质。

公开(公告)号：US4919731A

公开(公告)日：1990-04-24

申请号：US308450

申请日：1989-02-10

申请人： Kiyoshi Iyogi ,  Takaaki Yasumoto ,  Toshirou Yanazawa ,  Nobuo Iwase ,  Masako Nakahashi ,  Hiromitsu Takeda

发明人： Kiyoshi Iyogi ,  Takaaki Yasumoto ,  Toshirou Yanazawa ,  Nobuo Iwase ,  Masako Nakahashi ,  Hiromitsu Takeda

IPC分类号： H01R43/02 ,  B23K35/363 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H05K3/46

CPC分类号： H01L23/49827 ,  H01L21/4853 ,  H01L2924/00013 ,  H01L2924/0002 ,  Y10T29/49149

摘要： The present invention provides an electronic component part with terminal pins very closely and very strongly bonded to a high thermal conductivity ceramics circuit board and a method for simply and continuously manufacturing electronic component parts, with a high operability, each with terminal pins bonded to a high thermal conductivity ceramics circuit board. According to the present invention, an electronic component part is provided in which terminal pins are bonded to a high thermal conductivity ceramics circuit board by a brazing metal, containing at least one kind of Group IVa elements. In another aspect of the present invention a method is provided for manufacturing electronic component parts, which comprises the step of attaching terminal pins to a high thermal conductivity ceramics circuit board by a brazing paste layer comprised of brazing metal powder containing at least one kind of Group IVa elements, an acrylic binder with a carboxylic group as a substituent group and organic solvent, and heating the resultant structure in an atmosphere containing nitrogen as a principal element so that terminal pins are firmly bonded to a circuit board.

公开(公告)号：US4835344A

公开(公告)日：1989-05-30

申请号：US154273

申请日：1988-02-10

申请人： Kiyoshi Iyogi ,  Takaaki Yasumoto ,  Toshirou Yanazawa ,  Nobuo Iwase ,  Masako Nakahashi ,  Hiromitsu Takeda

发明人： Kiyoshi Iyogi ,  Takaaki Yasumoto ,  Toshirou Yanazawa ,  Nobuo Iwase ,  Masako Nakahashi ,  Hiromitsu Takeda

IPC分类号： H01R43/02 ,  B23K35/363 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H05K3/46

CPC分类号： H01L23/49827 ,  H01L21/4853 ,  H01L2924/00013 ,  H01L2924/0002 ,  Y10T29/49149

摘要： The present invention provides an electronic component part with terminal pins very closely and very strongly bonded to a high thermal conductivity ceramics circuit board and a method for simply and continuously manufacturing electronic component parts, with a high operability, each with terminal pins bonded to a high thermal conductivity ceramics circuit board. According to the present invention, an electronic component part is provided in which terminal pins are bonded to a high thermal conductivity ceramics circuit board by a brazing metal, containing at least one kind of Group IVa elements. In another aspect of the present invention a method is provided for manufacturing electronic component parts, which comprises the step of attaching terminal pins to a high thermal conductivity ceramics circuit board by a brazing paste layer comprised of brazing metal powder containing at least one kind of Group IVa elements, an acrylic binder with a carboxylic group as a substituent group and organic solvent, and heating the resultant structure in an atmosphere containing nitrogen as a principal element so that terminal pins are firmly bonded to a circuit board.

公开(公告)号：US4970571A

公开(公告)日：1990-11-13

申请号：US248101

申请日：1988-09-23

申请人： Koji Yamakawa ,  Nobuo Iwase ,  Michihiko Inaba

发明人： Koji Yamakawa ,  Nobuo Iwase ,  Michihiko Inaba

IPC分类号： H01L21/60

CPC分类号： H01L24/11 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1358 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014

摘要： According to the present invention, there is provided a method for forming a bump and comprising the steps of dipping a semiconductor element with an Al electrode and a passivation film formed thereon in a palladium solution containing 5 to 2,000 ppm of at least one element selected from the group consisting of Zn, Pb, Sn, Cd, and Cr, selectively precipitating palladium on the electrode, and conducting electroless nickel-plating on the semiconductor element, including the electrode on which palladium is precipitated.