公开(公告)号：US4970571A

公开(公告)日：1990-11-13

申请号：US248101

申请日：1988-09-23

申请人： Koji Yamakawa ,  Nobuo Iwase ,  Michihiko Inaba

发明人： Koji Yamakawa ,  Nobuo Iwase ,  Michihiko Inaba

IPC分类号： H01L21/60

CPC分类号： H01L24/11 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1358 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014

摘要： According to the present invention, there is provided a method for forming a bump and comprising the steps of dipping a semiconductor element with an Al electrode and a passivation film formed thereon in a palladium solution containing 5 to 2,000 ppm of at least one element selected from the group consisting of Zn, Pb, Sn, Cd, and Cr, selectively precipitating palladium on the electrode, and conducting electroless nickel-plating on the semiconductor element, including the electrode on which palladium is precipitated.

公开(公告)号：US4797530A

公开(公告)日：1989-01-10

申请号：US939969

申请日：1986-12-10

申请人： Nobuo Iwase

发明人： Nobuo Iwase

IPC分类号： H01L23/12 ,  C04B41/00 ,  C04B41/53 ,  C04B41/80 ,  C04B41/91 ,  H05K3/10 ,  B23K26/00

CPC分类号： C04B41/009 ,  C04B41/0036 ,  C04B41/53 ,  C04B41/80 ,  C04B41/91 ,  H05K3/105 ,  C04B2111/00844 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/49171 ,  H05K2203/107 ,  H05K2203/1136 ,  Y10T29/49155

摘要： A ceramic circuit substrate can be manufactured by a method comprising the steps of (i) providing an electrically insulating ceramic substrate; and (ii) irradiating a predetermined region of said ceramic substrate with an energy beam such that at least a portion of said region is rendered conductive.

摘要翻译： 陶瓷电路基板可以通过包括以下步骤的方法制造：（i）提供电绝缘陶瓷基板; 和（ii）用能量束照射所述陶瓷衬底的预定区域，使得所述区域的至少一部分变得导电。

公开(公告)号：US4659611A

公开(公告)日：1987-04-21

申请号：US706280

申请日：1985-02-27

申请人： Nobuo Iwase ,  Kazuo Anzai ,  Kazuo Shinozaki ,  Akihiko Tsuge ,  Kazutaka Saitoh ,  Kiyoshi Iyogi ,  Noboru Sato ,  Mitsuo Kasori

发明人： Nobuo Iwase ,  Kazuo Anzai ,  Kazuo Shinozaki ,  Akihiko Tsuge ,  Kazutaka Saitoh ,  Kiyoshi Iyogi ,  Noboru Sato ,  Mitsuo Kasori

IPC分类号： C04B41/51 ,  C04B41/52 ,  C04B41/88 ,  C04B41/89 ,  H01L23/15 ,  H01L23/373 ,  H05K1/03 ,  C04B35/52 ,  B32B5/16 ,  B32B15/04 ,  C04B35/58

CPC分类号： C04B41/009 ,  C04B41/5111 ,  C04B41/52 ,  C04B41/88 ,  C04B41/89 ,  H01L23/15 ,  H01L23/3731 ,  C04B2111/00844 ,  H01L2924/0002 ,  H05K1/0306 ,  Y10S428/901 ,  Y10T428/24917 ,  Y10T428/24926

摘要： A high thermal conductivity circuit substrate is provided comprising a sintered aluminum nitride ceramic substrate consisting essentially of one member selected from the group of yttrium, the rare earth metals and the alkali earth metals and an electrically conductive thick film paste for a conductive layer formed on the substrate.

摘要翻译： 提供了一种高导热性电路基板，其包括基本上由选自钇，稀土金属和碱土金属的一种元素组成的烧结氮化铝陶瓷基板，以及形成在导电层上的导电厚膜糊 基质。

公开(公告)号：US5909058A

公开(公告)日：1999-06-01

申请号：US934775

申请日：1997-09-22

申请人： Keiichi Yano ,  Hironori Asai ,  Kaoru Koiwa ,  Nobuo Iwase

发明人： Keiichi Yano ,  Hironori Asai ,  Kaoru Koiwa ,  Nobuo Iwase

IPC分类号： H01L23/24 ,  H01L23/498 ,  H01L23/34 ,  H01L23/29 ,  H01L23/48

CPC分类号： H01L23/49816 ,  H01L23/24 ,  H01L23/49833 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011

摘要： A thin type semiconductor package having a low thermal resistance and a low electric resistance is disclosed, that comprises a nitride ceramic supporting substrate having a first main surface and a second main surface, the nitride ceramic supporting substrate having via-holes that pass through from the first main surface to the second main surface, a resin film having a wiring layer, the resin film being bonded to the first main surface of the supporting substrate, the wiring layer being electrically connected to an edge portion of the via-holes on the first main surface, the resin film having an opening region, a semiconductor chip directly mounted on the first main surface of the nitride ceramic supporting substrate, disposed at the opening region of the resin film, and electrically connected to the wiring layer of the resin film, and external connection terminals disposed on the edge portion of the via-holes of the second main surface.

摘要翻译： 公开了一种具有低热阻和低电阻的薄型半导体封装，其包括具有第一主表面和第二主表面的氮化物陶瓷支撑衬底，所述氮化物陶瓷支撑衬底具有通孔， 第一主表面到第二主表面的树脂膜，具有布线层的树脂膜，树脂膜粘合到支撑基板的第一主表面，布线层电连接到第一主表面上的通孔的边缘部分 主表面，具有开口区域的树脂膜，直接安装在氮化物陶瓷支撑基板的第一主表面上的半导体芯片，设置在树脂膜的开口区域，并与树脂膜的布线层电连接， 以及设置在第二主表面的通孔的边缘部分上的外部连接端子。

公开(公告)号：US5622769A

公开(公告)日：1997-04-22

申请号：US194495

申请日：1994-02-10

申请人： Shoji Kozuka ,  Masaru Hayashi ,  Katsuyoshi Oh-Ishi ,  Takaaki Yasumoto ,  Nobuo Iwase ,  Hiroshi Endo ,  Koji Yamakawa ,  Kaoru Koiwa ,  Kiyoshi Iyogi

发明人： Shoji Kozuka ,  Masaru Hayashi ,  Katsuyoshi Oh-Ishi ,  Takaaki Yasumoto ,  Nobuo Iwase ,  Hiroshi Endo ,  Koji Yamakawa ,  Kaoru Koiwa ,  Kiyoshi Iyogi

IPC分类号： H01L23/15 ,  H05K1/03 ,  H05K3/38 ,  B32B3/00

CPC分类号： H05K3/38 ,  H01L23/15 ,  H01L2924/0002 ,  H05K1/0306 ,  Y10S428/901 ,  Y10T428/24917

摘要： According to this invention, there is disclosed a thermal conductivity substrate which includes an aluminum nitride sintered body and a coating layer formed on the body of aluminum phosphate and having a surface roughness of 1 .mu.m or less, and which has excellent humidity resistance and chemical resistance.

摘要翻译： 根据本发明，公开了一种导热性基材，其包括氮化铝烧结体和形成在磷酸铝体上的表面粗糙度为1μm以下并且具有优异的耐湿性和化学性质的涂层 抵抗性。

公开(公告)号：US5412160A

公开(公告)日：1995-05-02

申请号：US212869

申请日：1994-03-15

申请人： Takaaki Yasumoto ,  Nobuo Iwase ,  Kaoru Koiwa ,  Koji Yamakawa ,  Kiyoshi Iyogi

发明人： Takaaki Yasumoto ,  Nobuo Iwase ,  Kaoru Koiwa ,  Koji Yamakawa ,  Kiyoshi Iyogi

IPC分类号： H01L23/373 ,  H05K1/02 ,  H05K1/00

CPC分类号： H01L23/3731 ,  H01L23/3732 ,  H01L23/3733 ,  H05K1/024 ,  H05K3/4605 ,  H05K3/467 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K2201/0116 ,  H05K2201/0179

摘要： A circuit board comprising a substrate, at least one dielectric film formed on the substrate and made of at least one selected from the group consisting of AlN, BN, diamond, diamond-like carbon, BeO and SiC, the dielectric film having pores of a porosity of 5 to 95% by volume, and at least one wiring metal film formed on the dielectric film.

摘要翻译： 一种电路板，包括基板，至少一个电介质膜，形成在基板上，由选自AlN，BN，金刚石，类金刚石碳，BeO和SiC中的至少一种制成，电介质膜具有孔 5〜95体积％的孔隙率和形成在电介质膜上的至少一个布线金属膜。

公开(公告)号：US4916261A

公开(公告)日：1990-04-10

申请号：US648304

申请日：1984-09-07

申请人： Truong D. Thanh ,  Nobuo Iwase

发明人： Truong D. Thanh ,  Nobuo Iwase

IPC分类号： C04B35/01 ,  H05K1/03

CPC分类号： C04B35/01 ,  H05K1/0306

摘要： A circuit substrate comprises a sintered oxide body of barium, tin and boron as an insulating body which is able to be fired at a temperature less than 1300.degree. C. The circuit substrate is further improved in moisture resistance by containing titanium or securing substantially the composition of BaSn(BO.sub.3).sub.2.

摘要翻译： 电路基板包括作为绝缘体的钡，锡和硼的烧结氧化物体，其能够在低于1300℃的温度下被烧制。电路基板通过包含钛或基本上确保组合物进一步改善耐湿性 的BaSn（BO3）2。

公开(公告)号：US4855251A

公开(公告)日：1989-08-08

申请号：US267707

申请日：1988-11-03

申请人： Kiyoshi Iyogi ,  Koji Yamakawa ,  Nobuo Iwase

发明人： Kiyoshi Iyogi ,  Koji Yamakawa ,  Nobuo Iwase

IPC分类号： H01L21/60 ,  H01L23/485

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L2224/11003 ,  H01L2224/111 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2924/0001 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  Y10T29/49121

摘要： According to the present invention, a method is provided of manufacturing electronic parts, comprising a first step of forming on the surface of a substrate a bump wherein the metal particles of that portion of the bump which contacts the surface of the substrate have a larger diameter than the metal particles of that portion of the bump which does not contact the surface of the substrate, a second step of transferring the bump to an electrode lead, and a third step of connecting an electrode lead to a predetermined electrode section of the semiconductor chip, by means of the transferred bump. The method of the present invention ensures that the bump does not fall off during the electroplating and washing steps, and ensures a high-strength bond between the transferred bump and the electrode section of a semiconductor chip.

摘要翻译： 根据本发明，提供了一种制造电子部件的方法，该方法包括：在基板的表面上形成凸块的第一步骤，其中与基板表面接触的该凸块部分的金属颗粒具有较大的直径 比不与基板表面接触的部分凸块的金属颗粒，将凸点转移到电极引线的第二步骤，以及将电极引线连接到半导体芯片的预定电极部分的第三步骤 ，通过转移的凸块。 本发明的方法确保了在电镀和洗涤步骤期间凸起不会脱落，并确保了转印凸块与半导体芯片的电极部分之间的高强度结合。

公开(公告)号：US4835344A

公开(公告)日：1989-05-30

申请号：US154273

申请日：1988-02-10

申请人： Kiyoshi Iyogi ,  Takaaki Yasumoto ,  Toshirou Yanazawa ,  Nobuo Iwase ,  Masako Nakahashi ,  Hiromitsu Takeda

发明人： Kiyoshi Iyogi ,  Takaaki Yasumoto ,  Toshirou Yanazawa ,  Nobuo Iwase ,  Masako Nakahashi ,  Hiromitsu Takeda

IPC分类号： H01R43/02 ,  B23K35/363 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H05K3/46

CPC分类号： H01L23/49827 ,  H01L21/4853 ,  H01L2924/00013 ,  H01L2924/0002 ,  Y10T29/49149

摘要： The present invention provides an electronic component part with terminal pins very closely and very strongly bonded to a high thermal conductivity ceramics circuit board and a method for simply and continuously manufacturing electronic component parts, with a high operability, each with terminal pins bonded to a high thermal conductivity ceramics circuit board. According to the present invention, an electronic component part is provided in which terminal pins are bonded to a high thermal conductivity ceramics circuit board by a brazing metal, containing at least one kind of Group IVa elements. In another aspect of the present invention a method is provided for manufacturing electronic component parts, which comprises the step of attaching terminal pins to a high thermal conductivity ceramics circuit board by a brazing paste layer comprised of brazing metal powder containing at least one kind of Group IVa elements, an acrylic binder with a carboxylic group as a substituent group and organic solvent, and heating the resultant structure in an atmosphere containing nitrogen as a principal element so that terminal pins are firmly bonded to a circuit board.

公开(公告)号：US5453991A

公开(公告)日：1995-09-26

申请号：US31730

申请日：1993-03-15

申请人： Kouhei Suzuki ,  Kouji Suzuki ,  Miki Mori ,  Akinori Hongu ,  Nobuo Iwase

发明人： Kouhei Suzuki ,  Kouji Suzuki ,  Miki Mori ,  Akinori Hongu ,  Nobuo Iwase

IPC分类号： G06F11/273 ,  G06F7/02

CPC分类号： G06F11/2733

摘要： A highly-integrated semiconductor IC device includes a semiconductive substrate, on which an internal function circuit is arranged to have a first plurality of input terminals and a second plurality of output terminals. A logic circuit is arranged on the substrate and is connected to the internal circuit through the output terminals. The logic circuit has a third plurality of output terminals, which are less in number than the outputs of the internal circuit. These logic output terminals are coupled to the same number of inspection terminals, which are adapted to be coupled to a known electric inspection tool. The logic circuit processes the voltage signals appearing at the output terminals of the internal circuit so as to cause these signals to decrease in number. The output signals of the logic circuit are sent to the inspection terminals as monitor signals, based on which an inspection is carried out to determine whether the internal circuit operates normally.

摘要翻译： 高度集成的半导体IC器件包括半导体衬底，内部功能电路布置成具有第一多个输入端子和第二多个输出端子。 逻辑电路布置在基板上，并通过输出端子连接到内部电路。 逻辑电路具有第三多个输出端子，其数量小于内部电路的输出。 这些逻辑输出端子被耦合到相同数量的检查端子，这些检查端子适于联接到已知的电气检查工具。 逻辑电路处理出现在内部电路的输出端子处的电压信号，从而使这些信号数量减少。 逻辑电路的输出信号作为监视信号发送到检查端子，由此执行检查以确定内部电路是否正常工作。