公开(公告)号：US08148809B2

公开(公告)日：2012-04-03

申请号：US12654707

申请日：2009-12-29

申请人： Kouji Senda ,  Satoshi Shiraki ,  Yukihiro Maeda ,  Shinichi Hirose ,  Tetsuo Fujii ,  Takashi Nakano

发明人： Kouji Senda ,  Satoshi Shiraki ,  Yukihiro Maeda ,  Shinichi Hirose ,  Tetsuo Fujii ,  Takashi Nakano

IPC分类号： H01L23/48

CPC分类号： H01L21/84 ,  H01L23/3107 ,  H01L23/4951 ,  H01L23/49551 ,  H01L24/27 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method for manufacturing a semiconductor device includes: preparing a wafer formed of a SOI substrate; forming a circuit portion in a principal surface portion; removing a support substrate of the SOI substrate; fixing an insulation member on a backside of a semiconductor layer so as to be opposite to the circuit portion; dicing the wafer and dividing the wafer into multiple chips; arranging a first conductive member on the insulation member so as to be opposite to a part of the low potential reference circuit, and arranging a second conductive member on the insulation member so as to be opposite to a part of the high potential reference circuit; and coupling the first conductive member with a first part of the low potential reference circuit, and coupling the second conductive member with a second part of the high potential reference circuit.

摘要翻译： 一种制造半导体器件的方法包括：制备由SOI衬底形成的晶片; 在主表面部分形成电路部分; 去除SOI衬底的支撑衬底; 将绝缘构件固定在半导体层的背面以与电路部分相对; 切割晶片并将晶片分成多个芯片; 在所述绝缘构件上设置与所述低电位基准电路的一部分相对的第一导电构件，并且在所述绝缘构件上配置与所述高电位基准电路的一部分相反的第二导电构件; 以及将所述第一导电构件与所述低电位参考电路的第一部分耦合，以及将所述第二导电构件与所述高电位参考电路的第二部分耦合。

公开(公告)号：US20100176480A1

公开(公告)日：2010-07-15

申请号：US12654707

申请日：2009-12-29

申请人： Kouji Senda ,  Satoshi Shiraki ,  Yukihiro Maeda ,  Shinichi Hirose ,  Tetsuo Fujii ,  Takashi Nakano

发明人： Kouji Senda ,  Satoshi Shiraki ,  Yukihiro Maeda ,  Shinichi Hirose ,  Tetsuo Fujii ,  Takashi Nakano

IPC分类号： H01L27/06 ,  H01L21/78

CPC分类号： H01L21/84 ,  H01L23/3107 ,  H01L23/4951 ,  H01L23/49551 ,  H01L24/27 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method for manufacturing a semiconductor device includes: preparing a wafer formed of a SOI substrate; forming a circuit portion in a principal surface portion; removing a support substrate of the SOI substrate; fixing an insulation member on a backside of a semiconductor layer so as to be opposite to the circuit portion; dicing the wafer and dividing the wafer into multiple chips; arranging a first conductive member on the insulation member so as to be opposite to a part of the low potential reference circuit, and arranging a second conductive member on the insulation member so as to be opposite to a part of the high potential reference circuit; and coupling the first conductive member with a first part of the low potential reference circuit, and coupling the second conductive member with a second part of the high potential reference circuit.

摘要翻译： 一种制造半导体器件的方法包括：制备由SOI衬底形成的晶片; 在主表面部分形成电路部分; 去除SOI衬底的支撑衬底; 将绝缘构件固定在半导体层的背面以与电路部分相对; 切割晶片并将晶片分成多个芯片; 在所述绝缘构件上设置与所述低电位基准电路的一部分相对的第一导电构件，并且在所述绝缘构件上配置与所述高电位基准电路的一部分相反的第二导电构件; 以及将所述第一导电构件与所述低电位参考电路的第一部分耦合，以及将所述第二导电构件与所述高电位参考电路的第二部分耦合。

公开(公告)号：US20050001265A1

公开(公告)日：2005-01-06

申请号：US10864518

申请日：2004-06-10

申请人： Satoshi Shiraki ,  Yoshiaki Nakayama ,  Shoji Mizuno ,  Takashi Nakano ,  Akira Yamada

发明人： Satoshi Shiraki ,  Yoshiaki Nakayama ,  Shoji Mizuno ,  Takashi Nakano ,  Akira Yamada

IPC分类号： H01L21/76 ,  H01L21/336 ,  H01L21/763 ,  H01L21/8234 ,  H01L27/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L29/76

CPC分类号： H01L29/7824 ,  H01L21/26586 ,  H01L21/76286 ,  H01L21/763 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823481 ,  H01L29/0696 ,  H01L29/1041 ,  H01L29/105 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66681 ,  H01L29/66795 ,  H01L29/7825 ,  H01L29/7831 ,  H01L29/7835

摘要： A semiconductor device includes: a semiconductor substrate with a principal plane; a base region disposed on the principal plane; a source region disposed on the principal plane in the base region to be shallower than the base region; a drain region disposed on the principal plane, and spaced to the base region; a trench disposed on the principal plane; a trench gate electrode disposed in the trench through a trench gate insulation film; a planer gate electrode disposed on the principal plane of the semiconductor substrate through a planer gate insulation film; and an impurity diffusion region having high concentration of impurities and disposed in a portion of the base region to be a channel region facing the planer gate electrode.

摘要翻译： 半导体器件包括：具有主平面的半导体衬底; 设置在主平面上的基部区域; 源区域，其设置在所述基底区域中的所述主平面上，以比所述基底区域浅; 漏极区域，设置在所述主平面上，并且与所述基极区域间隔开; 设在主平面上的沟槽; 通过沟槽栅极绝缘膜设置在沟槽中的沟槽栅电极; 通过平面栅极绝缘膜设置在半导体衬底的主平面上的平面栅电极; 以及杂质扩散区域，其具有高浓度的杂质，并且设置在基极区域的一部分中，作为面向平面栅电极的沟道区域。

公开(公告)号：US20080293202A1

公开(公告)日：2008-11-27

申请号：US12219008

申请日：2008-07-15

申请人： Satoshi Shiraki ,  Yoshiaki Nakayama ,  Shoji Mizuno ,  Takashi Nakano ,  Akira Yamada

发明人： Satoshi Shiraki ,  Yoshiaki Nakayama ,  Shoji Mizuno ,  Takashi Nakano ,  Akira Yamada

IPC分类号： H01L21/336

CPC分类号： H01L29/7824 ,  H01L21/26586 ,  H01L21/76286 ,  H01L21/763 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823481 ,  H01L29/0696 ,  H01L29/1041 ,  H01L29/105 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66681 ,  H01L29/66795 ,  H01L29/7825 ,  H01L29/7831 ,  H01L29/7835

摘要： A semiconductor device includes: a semiconductor substrate with a principal plane; a base region disposed on the principal plane; a source region disposed on the principal plane in the base region to be shallower than the base region; a drain region disposed on the principal plane, and spaced to the base region; a trench disposed on the principal plane; a trench gate electrode disposed in the trench through a trench gate insulation film; a planer gate electrode disposed on the principal plane of the semiconductor substrate through a planer gate insulation film; and an impurity diffusion region having high concentration of impurities and disposed in a portion of the base region to be a channel region facing the planer gate electrode.

摘要翻译： 半导体器件包括：具有主平面的半导体衬底; 设置在主平面上的基部区域; 源区域，其设置在所述基底区域中的所述主平面上，以比所述基底区域浅; 漏极区域，设置在所述主平面上，并且与所述基极区域间隔开; 设在主平面上的沟槽; 通过沟槽栅极绝缘膜设置在沟槽中的沟槽栅电极; 通过平面栅极绝缘膜设置在半导体衬底的主平面上的平面栅电极; 以及杂质扩散区域，其具有高浓度的杂质，并且设置在基极区域的一部分中，作为面向平面栅电极的沟道区域。

公开(公告)号：US07109558B2

公开(公告)日：2006-09-19

申请号：US10160098

申请日：2002-06-04

申请人： Takashi Nakano ,  Satoshi Shiraki ,  Yutaka Fukuda ,  Nobumasa Ueda ,  Shoji Miura

发明人： Takashi Nakano ,  Satoshi Shiraki ,  Yutaka Fukuda ,  Nobumasa Ueda ,  Shoji Miura

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7811 ,  H01L23/4824 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/7802 ,  H01L29/7816 ,  H01L29/7835 ,  Y10S257/901

摘要： A power MOS transistor formed of an array of source cells and drain cells on an IC chip substrate has a plurality of substrate contact cells, each formed external to the source cells, having respective substrate potential-setting electrodes to which an externally supplied substrate bias voltage can be applied, enabling the substrate potential to be set independently of the source potential of the transistor. It thereby becomes possible to modify the threshold voltage of the transistor or maintain a constant potential difference between the substrate potential and that of a gate input signal. Since the requirement for a substrate contact region within each source cell is eliminated, and the number of substrate contact cells can be fewer than that of the source cells, the chip area occupied by the transistor can be reduced by comparison with a prior art configuration providing such a substrate potential control capability.

公开(公告)号：US07799667B2

公开(公告)日：2010-09-21

申请号：US12219008

申请日：2008-07-15

申请人： Satoshi Shiraki ,  Yoshiaki Nakayama ,  Shoji Mizuno ,  Takashi Nakano ,  Akira Yamada

发明人： Satoshi Shiraki ,  Yoshiaki Nakayama ,  Shoji Mizuno ,  Takashi Nakano ,  Akira Yamada

IPC分类号： H01L21/336

CPC分类号： H01L29/7824 ,  H01L21/26586 ,  H01L21/76286 ,  H01L21/763 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823481 ,  H01L29/0696 ,  H01L29/1041 ,  H01L29/105 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66681 ,  H01L29/66795 ,  H01L29/7825 ,  H01L29/7831 ,  H01L29/7835

摘要： A semiconductor device includes: a semiconductor substrate with a principal plane; a base region disposed on the principal plane; a source region disposed on the principal plane in the base region to be shallower than the base region; a drain region disposed on the principal plane, and spaced to the base region; a trench disposed on the principal plane; a trench gate electrode disposed in the trench through a trench gate insulation film; a planer gate electrode disposed on the principal plane of the semiconductor substrate through a planer gate insulation film; and an impurity diffusion region having high concentration of impurities and disposed in a portion of the base region to be a channel region facing the planer gate electrode.

摘要翻译： 半导体器件包括：具有主平面的半导体衬底; 设置在主平面上的基部区域; 源区域，其设置在所述基底区域中的所述主平面上，以比所述基底区域浅; 漏极区域，设置在所述主平面上，并且与所述基极区域间隔开; 设在主平面上的沟槽; 通过沟槽栅极绝缘膜设置在沟槽中的沟槽栅电极; 通过平面栅极绝缘膜设置在半导体衬底的主平面上的平面栅电极; 以及杂质扩散区域，其具有高浓度的杂质，并且设置在基极区域的一部分中，作为面向平面栅电极的沟道区域。

公开(公告)号：US20080230834A1

公开(公告)日：2008-09-25

申请号：US12071411

申请日：2008-02-21

申请人： Nozomu Akagi ,  Shigeki Takahashi ,  Takashi Nakano ,  Yasushi Higuchi ,  Tetsuo Fujii ,  Yoshiyuki Hattori ,  Makoto Kuwahara

发明人： Nozomu Akagi ,  Shigeki Takahashi ,  Takashi Nakano ,  Yasushi Higuchi ,  Tetsuo Fujii ,  Yoshiyuki Hattori ,  Makoto Kuwahara

IPC分类号： H01L27/06

CPC分类号： H01L29/7817 ,  H01L27/0738 ,  H01L29/0696 ,  H01L29/41758 ,  H01L29/42368 ,  H01L29/435 ,  H01L29/4933 ,  H01L29/7824 ,  H01L29/7835

摘要： A semiconductor apparatus comprises: a semiconductor substrate; and a lateral type MIS transistor disposed on a surface part of the semiconductor substrate. The lateral type MIS transistor includes: a line coupled with a gate of the lateral type MIS transistor; a polycrystalline silicon resistor that is provided in the line, and that has a conductivity type opposite to a drain of the lateral type MIS transistor; and an insulating layer through which a drain voltage of the lateral type MIS transistor is applied to the polycrystalline silicon resistor.

摘要翻译： 半导体装置包括：半导体衬底; 以及设置在半导体衬底的表面部分上的横向型MIS晶体管。 横向型MIS晶体管包括：与横向型MIS晶体管的栅极耦合的线; 该多晶硅电阻器设置在该线路中，并且具有与横向型MIS晶体管的漏极相反的导电类型; 以及绝缘层，横向型MIS晶体管的漏极电压通过该绝缘层施加到多晶硅电阻器。

公开(公告)号：US20080054325A1

公开(公告)日：2008-03-06

申请号：US11892819

申请日：2007-08-28

申请人： Shigeki Takahashi ,  Takashi Nakano ,  Nozomu Akagi ,  Yasushi Higuchi ,  Tetsuo Fujii ,  Yoshiyuki Hattori ,  Makoto Kuwahara ,  Kyoko Okada

发明人： Shigeki Takahashi ,  Takashi Nakano ,  Nozomu Akagi ,  Yasushi Higuchi ,  Tetsuo Fujii ,  Yoshiyuki Hattori ,  Makoto Kuwahara ,  Kyoko Okada

IPC分类号： H01L27/06

CPC分类号： H01L27/0727 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/42356 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/7817 ,  H01L29/7821

摘要： A semiconductor device includes: a semiconductor substrate; a lateral MOS transistor disposed in the substrate; a Zener diode disposed in the substrate; and a capacitor disposed in the substrate. The transistor includes a drain and a gate, and the diode and the capacitor are coupled in series between the drain and the gate. This device has minimized dimensions and high switching speed. Further, both of a switching loss and a surge voltage are improved.

摘要翻译： 半导体器件包括：半导体衬底; 设置在基板中的横向MOS晶体管; 设置在基板中的齐纳二极管; 以及设置在基板中的电容器。 晶体管包括漏极和栅极，并且二极管和电容器串联耦合在漏极和栅极之间。 该设备具有最小的尺寸和高切换速度。 此外，改善了开关损耗和浪涌电压两者。

公开(公告)号：US08022477B2

公开(公告)日：2011-09-20

申请号：US12071411

申请日：2008-02-21

申请人： Nozomu Akagi ,  Shigeki Takahashi ,  Takashi Nakano ,  Yasushi Higuchi ,  Tetsuo Fujii ,  Yoshiyuki Hattori ,  Makoto Kuwahara

发明人： Nozomu Akagi ,  Shigeki Takahashi ,  Takashi Nakano ,  Yasushi Higuchi ,  Tetsuo Fujii ,  Yoshiyuki Hattori ,  Makoto Kuwahara

IPC分类号： H01L29/66

CPC分类号： H01L29/7817 ,  H01L27/0738 ,  H01L29/0696 ,  H01L29/41758 ,  H01L29/42368 ,  H01L29/435 ,  H01L29/4933 ,  H01L29/7824 ,  H01L29/7835

摘要： A semiconductor apparatus comprises: a semiconductor substrate; and a lateral type MIS transistor disposed on a surface part of the semiconductor substrate. The lateral type MIS transistor includes: a line coupled with a gate of the lateral type MIS transistor; a polycrystalline silicon resistor that is provided in the line, and that has a conductivity type opposite to a drain of the lateral type MIS transistor; and an insulating layer through which a drain voltage of the lateral type MIS transistor is applied to the polycrystalline silicon resistor.

摘要翻译： 半导体装置包括：半导体衬底; 以及设置在半导体衬底的表面部分上的横向型MIS晶体管。 横向型MIS晶体管包括：与横向型MIS晶体管的栅极耦合的线; 该多晶硅电阻器设置在该线路中，并且具有与横向型MIS晶体管的漏极相反的导电类型; 以及绝缘层，横向型MIS晶体管的漏极电压通过该绝缘层施加到多晶硅电阻器。

公开(公告)号：US07893458B2

公开(公告)日：2011-02-22

申请号：US11892819

申请日：2007-08-28

申请人： Shigeki Takahashi ,  Takashi Nakano ,  Nozomu Akagi ,  Yasushi Higuchi ,  Tetsuo Fujii ,  Yoshiyuki Hattori ,  Makoto Kuwahara ,  Kyoko Okada

发明人： Shigeki Takahashi ,  Takashi Nakano ,  Nozomu Akagi ,  Yasushi Higuchi ,  Tetsuo Fujii ,  Yoshiyuki Hattori ,  Makoto Kuwahara ,  Kyoko Okada

IPC分类号： H01L29/74 ,  H01L29/76

CPC分类号： H01L27/0727 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/42356 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/7817 ,  H01L29/7821

摘要： A semiconductor device includes: a semiconductor substrate; a lateral MOS transistor disposed in the substrate; a Zener diode disposed in the substrate; and a capacitor disposed in the substrate. The transistor includes a drain and a gate, and the diode and the capacitor are coupled in series between the drain and the gate. This device has minimized dimensions and high switching speed. Further, both of a switching loss and a surge voltage are improved.

摘要翻译： 半导体器件包括：半导体衬底; 设置在基板中的横向MOS晶体管; 设置在基板中的齐纳二极管; 以及设置在基板中的电容器。 晶体管包括漏极和栅极，并且二极管和电容器串联耦合在漏极和栅极之间。 该设备具有最小的尺寸和高切换速度。 此外，改善了开关损耗和浪涌电压两者。