公开(公告)号：US20080023846A1

公开(公告)日：2008-01-31

申请号：US11878796

申请日：2007-07-26

申请人： Katsuyuki Seki ,  Akira Suzuki ,  Koujiro Kameyama ,  Takahiro Oikawa

发明人： Katsuyuki Seki ,  Akira Suzuki ,  Koujiro Kameyama ,  Takahiro Oikawa

IPC分类号： H01L21/311 ,  H01L21/302 ,  H01L23/48

CPC分类号： H01L21/3065 ,  H01L21/30655 ,  H01L21/31138 ,  H01L21/76898 ,  H01L2224/02372 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/05147 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/16 ,  H01L2924/01004 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/0496 ,  H01L2924/01074 ,  H01L2924/0494

摘要： The invention provides a method of manufacturing a semiconductor device which achieves high reliability and high yield as well as high production efficiency. Back surface grinding (back grinding) is performed to a semiconductor substrate to thin the semiconductor substrate. A damaged layer formed by the back surface grinding is not removed at this time, and a photoresist layer is selectively formed on the back surface of the semiconductor substrate. The semiconductor substrate is then etched using the photoresist layer as a mask to form a via hole. The photoresist layer is then removed with the semiconductor substrate still placed in an etcher used in the etching process subsequently after the formation of the via hole. In this manner, the etching process and the next ashing process are performed sequentially in one apparatus. Then a process of removing the damaged layer on the back surface of the semiconductor substrate and a process of smoothing the sidewall of the via hole are simultaneously performed subsequently after the ashing process in the same apparatus.

摘要翻译： 本发明提供一种制造半导体器件的方法，该方法实现了高可靠性和高产率以及高生产效率。 对半导体基板进行背面研磨（背面研磨）以使半导体基板变薄。 此时不会去除由背面磨削形成的损伤层，并且在半导体衬底的背面上选择性地形成光致抗蚀剂层。 然后使用光致抗蚀剂层作为掩模蚀刻半导体衬底以形成通孔。 然后在形成通孔之后，半导体衬底仍然放置在蚀刻工艺中使用的蚀刻器中，去除光致抗蚀剂层。 以这种方式，在一个装置中顺序地执行蚀刻处理和下一个灰化处理。 然后，在同一装置的灰化处理之后，随后进行去除半导体基板背面的损伤层的工序和平滑通路孔的侧面的工序。

公开(公告)号：US20070166957A1

公开(公告)日：2007-07-19

申请号：US11645811

申请日：2006-12-27

申请人： Koujiro Kameyama ,  Akira Suzuki ,  Takahiro Oikawa

发明人： Koujiro Kameyama ,  Akira Suzuki ,  Takahiro Oikawa

IPC分类号： H01L21/30

CPC分类号： H01L21/76898 ,  H01L21/78 ,  H01L23/481 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/06181 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2924/09701

摘要： The invention is directed to enhancement of reliability and a yield of a semiconductor device by a method of manufacturing the semiconductor device with a supporting body without making the process complex. A second insulation film, a semiconductor substrate, a first insulation film, and a passivation film are etched and removed in this order using a resist layer or a protection layer as a mask. By this etching, an adhesive layer is partially exposed in an opening. At this time, a number of semiconductor devices are separated in individual semiconductor dies. Then, as shown in FIG. 10, a solvent (e.g. alcohol or acetone) is supplied to the exposed adhesive layer through the opening to gradually reduce its adhesion and thereby a supporting body is removed from the semiconductor substrate.

摘要翻译： 本发明旨在通过一种制造具有支撑体的半导体器件的方法来提高半导体器件的可靠性和成品率，而不会使工艺复杂化。 使用抗蚀剂层或保护层作为掩模，依次蚀刻除去第二绝缘膜，半导体基板，第一绝缘膜和钝化膜。 通过该蚀刻，粘合剂层部分地暴露在开口中。 此时，在各个半导体管芯中分离出多个半导体器件。 然后，如图1所示。 如图10所示，通过开口将溶剂（例如醇或丙酮）供给到暴露的粘合剂层，以逐渐降低其粘附性，从而从半导体衬底去除支撑体。

公开(公告)号：US08173543B2

公开(公告)日：2012-05-08

申请号：US11878796

申请日：2007-07-26

申请人： Katsuyuki Seki ,  Akira Suzuki ,  Koujiro Kameyama ,  Takahiro Oikawa

发明人： Katsuyuki Seki ,  Akira Suzuki ,  Koujiro Kameyama ,  Takahiro Oikawa

IPC分类号： H01L21/44 ,  H01L21/311

CPC分类号： H01L21/3065 ,  H01L21/30655 ,  H01L21/31138 ,  H01L21/76898 ,  H01L2224/02372 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/05147 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/16 ,  H01L2924/01004 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/0496 ,  H01L2924/01074 ,  H01L2924/0494

摘要： The invention provides a method of manufacturing a semiconductor device which achieves high reliability and high yield as well as high production efficiency. Back surface grinding (back grinding) is performed to a semiconductor substrate to thin the semiconductor substrate. A damaged layer formed by the back surface grinding is not removed at this time, and a photoresist layer is selectively formed on the back surface of the semiconductor substrate. The semiconductor substrate is then etched using the photoresist layer as a mask to form a via hole. The photoresist layer is then removed with the semiconductor substrate still placed in an etcher used in the etching process subsequently after the formation of the via hole. In this manner, the etching process and the next ashing process are performed sequentially in one apparatus. Then a process of removing the damaged layer on the back surface of the semiconductor substrate and a process of smoothing the sidewall of the via hole are simultaneously performed subsequently after the ashing process in the same apparatus.

摘要翻译： 本发明提供一种制造半导体器件的方法，该方法实现了高可靠性和高产率以及高生产效率。 对半导体基板进行背面研磨（背面研磨）以使半导体基板变薄。 此时不会去除由背面磨削形成的损伤层，并且在半导体衬底的背面上选择性地形成光致抗蚀剂层。 然后使用光致抗蚀剂层作为掩模蚀刻半导体衬底以形成通孔。 然后在形成通孔之后，半导体衬底仍然放置在蚀刻工艺中使用的蚀刻器中，去除光致抗蚀剂层。 以这种方式，在一个装置中顺序地执行蚀刻处理和下一个灰化处理。 然后，在同一装置的灰化处理之后，随后进行去除半导体基板背面的损伤层的工序和平滑通路孔的侧面的工序。

公开(公告)号：US08669183B2

公开(公告)日：2014-03-11

申请号：US11802107

申请日：2007-05-18

申请人： Akira Suzuki ,  Katsuyuki Seki ,  Koujiro Kameyama ,  Takahiro Oikawa

发明人： Akira Suzuki ,  Katsuyuki Seki ,  Koujiro Kameyama ,  Takahiro Oikawa

IPC分类号： H01L21/302

CPC分类号： H01L21/30655 ,  H01L21/76898 ,  H01L2224/02372 ,  H01L2224/05548 ,  H01L2924/0002 ,  H01L2924/00

摘要： This invention is directed to form a homogeneous film in a via hole formed in a semiconductor device using Bosch process. The via hole that penetrates through a predetermined region in a semiconductor substrate is formed by etching the semiconductor substrate from one of its surface to the other by the Bosch process using a mask layer as a mask. Next, the mask layer is removed. Then, scallops are removed by dry etching to flatten a sidewall of the via hole. Following the above, an insulation film, a barrier layer and the like are formed homogeneously in the via hole.

摘要翻译： 本发明涉及在使用博世工艺的半导体器件中形成的通孔中形成均匀的膜。 穿过半导体衬底中的预定区域的通孔是通过使用掩模层作为掩模的博世工艺将半导体衬底从其表面之一蚀刻到另一表面而形成的。 接下来，去除掩模层。 然后，通过干法蚀刻除去扇贝，使通孔的侧壁变平。 接下来，在通孔中均匀地形成绝缘膜，阻挡层等。

公开(公告)号：US07795115B2

公开(公告)日：2010-09-14

申请号：US11645811

申请日：2006-12-27

申请人： Koujiro Kameyama ,  Akira Suzuki ,  Takahiro Oikawa

发明人： Koujiro Kameyama ,  Akira Suzuki ,  Takahiro Oikawa

IPC分类号： H01L21/00

CPC分类号： H01L21/76898 ,  H01L21/78 ,  H01L23/481 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/06181 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2924/09701

摘要： The invention is directed to enhancement of reliability and a yield of a semiconductor device by a method of manufacturing the semiconductor device with a supporting body without making the process complex. A second insulation film, a semiconductor substrate, a first insulation film, and a passivation film are etched and removed in this order using a resist layer or a protection layer as a mask. By this etching, an adhesive layer is partially exposed in an opening. At this time, a number of semiconductor devices are separated in individual semiconductor dies. Then, as shown in FIG. 10, a solvent (e.g. alcohol or acetone) is supplied to the exposed adhesive layer through the opening to gradually reduce its adhesion and thereby a supporting body is removed from the semiconductor substrate.

摘要翻译： 本发明旨在通过一种制造具有支撑体的半导体器件的方法来提高半导体器件的可靠性和成品率，而不会使工艺复杂化。 使用抗蚀剂层或保护层作为掩模，依次蚀刻除去第二绝缘膜，半导体基板，第一绝缘膜和钝化膜。 通过该蚀刻，粘合剂层部分地暴露在开口中。 此时，在各个半导体管芯中分离出多个半导体器件。 然后，如图1所示。 如图10所示，通过开口将溶剂（例如醇或丙酮）供给到暴露的粘合剂层，以逐渐降低其粘附性，从而从半导体衬底去除支撑体。

公开(公告)号：US20070281474A1

公开(公告)日：2007-12-06

申请号：US11802107

申请日：2007-05-18

申请人： Akira Suzuki ,  Katsuyuki Seki ,  Koujiro Kameyama ,  Takahiro Oikawa

发明人： Akira Suzuki ,  Katsuyuki Seki ,  Koujiro Kameyama ,  Takahiro Oikawa

IPC分类号： H01L21/3065

CPC分类号： H01L21/30655 ,  H01L21/76898 ,  H01L2224/02372 ,  H01L2224/05548 ,  H01L2924/0002 ,  H01L2924/00

摘要： This invention is directed to form a homogeneous film in a via hole formed in a semiconductor device using Bosch process. The via hole that penetrates through a predetermined region in a semiconductor substrate is formed by etching the semiconductor substrate from one of its surface to the other by the Bosch process using a mask layer as a mask. Next, the mask layer is removed. Then, scallops are removed by dry etching to flatten a sidewall of the via hole. Following the above, an insulation film, a barrier layer and the like are formed homogeneously in the via hole.

摘要翻译： 本发明涉及在使用博世工艺的半导体器件中形成的通孔中形成均匀的膜。 穿过半导体衬底中的预定区域的通孔是通过使用掩模层作为掩模的博世工艺将半导体衬底从其表面之一蚀刻到另一表面而形成的。 接下来，去除掩模层。 然后，通过干法蚀刻除去扇贝，使通孔的侧壁变平。 接下来，在通孔中均匀地形成绝缘膜，阻挡层等。

公开(公告)号：US20100052090A1

公开(公告)日：2010-03-04

申请号：US12538635

申请日：2009-08-10

申请人： Akira Suzuki ,  Naofumi Tsuchiya ,  Koujiro Kameyama

发明人： Akira Suzuki ,  Naofumi Tsuchiya ,  Koujiro Kameyama

IPC分类号： H01L29/06 ,  H01L21/762

CPC分类号： H01L29/8611 ,  H01L21/76229 ,  H01L29/0615 ,  H01L29/7322

摘要： The invention is directed to reduction of a manufacturing cost and enhancement of a breakdown voltage of a PN junction portion abutting on a guard ring. An N− type semiconductor layer is formed on a front surface of a semiconductor substrate, and a P type semiconductor layer is formed thereon. An insulation film is formed on the P type semiconductor layer. Then, a plurality of grooves, i.e., a first groove, a second groove and a third groove are formed from the insulation film to the middle of the N− type semiconductor layer in the thickness direction thereof. The plurality of grooves is formed so that one of the two grooves next to each other among these, that is closer to an electronic device, i.e., to an anode electrode, is formed shallower than the other located on the outside of the one. Then, an insulating material is deposited in the first groove, the second groove and the third groove. The lamination body of the semiconductor substrate and the layers laminated thereon is then diced along dicing lines.

摘要翻译： 本发明旨在降低制造成本和提高邻接在保护环上的PN结部分的击穿电压。 在半导体衬底的前表面上形成N-型半导体层，并在其上形成P型半导体层。 在P型半导体层上形成绝缘膜。 然后，从绝缘膜到N型半导体层的厚度方向的中间形成有多个槽，即第一槽，第二槽和第三槽。 多个槽形成为使得彼此相邻的两个凹槽中的一个更靠近电子器件即阳极电极的形状比位于该外部的另一个凹槽更浅。 然后，绝缘材料沉积在第一槽，第二槽和第三槽中。 然后将半导体衬底的层压体和层压在其上的层切割成切割线。

公开(公告)号：US20050269704A1

公开(公告)日：2005-12-08

申请号：US11054603

申请日：2005-02-10

申请人： Koujiro Kameyama ,  Akira Suzuki ,  Yoshio Okayama

发明人： Koujiro Kameyama ,  Akira Suzuki ,  Yoshio Okayama

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/768 ,  H01L23/12 ,  H01L23/48 ,  H01L29/74 ,  H01L21/4763

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L27/14683 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05181 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/04941 ,  H01L2924/3025 ,  H01L2924/00014

摘要： This invention provides a semiconductor device and a manufacturing method thereof which can minimize deterioration of electric characteristics of the semiconductor device without increasing an etching process. In the semiconductor device of the invention, a pad electrode layer formed of a first barrier layer and an aluminum layer laminated thereon is formed on a top surface of a semiconductor substrate. A supporting substrate is further attached on the top surface of the semiconductor substrate. A second barrier layer is formed on a back surface of the semiconductor substrate and in a via hole formed from the back surface of the semiconductor substrate to the first barrier layer. Furthermore, a re-distribution layer is formed in the via hole so as to completely fill the via hole or so as not to completely fill the via hole. A ball-shaped terminal is formed on the re-distribution layer.

摘要翻译： 本发明提供一种半导体器件及其制造方法，其可以在不增加蚀刻工艺的情况下最小化半导体器件的电特性的劣化。 在本发明的半导体器件中，在半导体衬底的顶表面上形成由第一阻挡层和层叠在其上的铝层形成的焊盘电极层。 支撑衬底进一步附着在半导体衬底的顶表面上。 第二阻挡层形成在半导体衬底的背面和从半导体衬底的背面形成到第一阻挡层的通孔中。 此外，在通孔中形成再分布层，以便完全填充通孔或不完全填充通孔。 在再分配层上形成有球状的端子。

公开(公告)号：US08148788B2

公开(公告)日：2012-04-03

申请号：US12538635

申请日：2009-08-10

申请人： Akira Suzuki ,  Naofumi Tsuchiya ,  Koujiro Kameyama

发明人： Akira Suzuki ,  Naofumi Tsuchiya ,  Koujiro Kameyama

IPC分类号： H01L21/762

CPC分类号： H01L29/8611 ,  H01L21/76229 ,  H01L29/0615 ,  H01L29/7322

摘要： The invention is directed to reduction of a manufacturing cost and enhancement of a breakdown voltage of a PN junction portion abutting on a guard ring. An N− type semiconductor layer is formed on a front surface of a semiconductor substrate, and a P type semiconductor layer is formed thereon. An insulation film is formed on the P type semiconductor layer. Then, a plurality of grooves, i.e., a first groove, a second groove and a third groove are formed from the insulation film to the middle of the N− type semiconductor layer in the thickness direction thereof. The plurality of grooves is formed so that one of the two grooves next to each other among these, that is closer to an electronic device, i.e., to an anode electrode, is formed shallower than the other located on the outside of the one. Then, an insulating material is deposited in the first groove, the second groove and the third groove. The lamination body of the semiconductor substrate and the layers laminated thereon is then diced along dicing lines.

摘要翻译： 本发明旨在降低制造成本和提高邻接在保护环上的PN结部分的击穿电压。 在半导体衬底的前表面上形成N-型半导体层，并在其上形成P型半导体层。 在P型半导体层上形成绝缘膜。 然后，从绝缘膜到N型半导体层的厚度方向的中间形成有多个槽，即第一槽，第二槽和第三槽。 多个槽形成为使得彼此相邻的两个凹槽中的一个更靠近电子器件即阳极电极的形状比位于该外部的另一个凹槽更浅。 然后，绝缘材料沉积在第一槽，第二槽和第三槽中。 然后将半导体衬底的层压体和层压在其上的层切割成切割线。

公开(公告)号：US07750478B2

公开(公告)日：2010-07-06

申请号：US11808667

申请日：2007-06-12

申请人： Koujiro Kameyama ,  Akira Suzuki ,  Yoshio Okayama ,  Mitsuo Umemoto ,  Kenji Takahashi ,  Hiroshi Terao ,  Masataka Hoshino

发明人： Koujiro Kameyama ,  Akira Suzuki ,  Yoshio Okayama ,  Mitsuo Umemoto ,  Kenji Takahashi ,  Hiroshi Terao ,  Masataka Hoshino

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/12 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05548 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2224/05599

摘要： A semiconductor device with improved reliability and its manufacturing method is offered. The semiconductor device of this invention includes a semiconductor substrate, a pad electrode formed on the semiconductor substrate through an insulation layer made of silicon oxide, silicon nitride or the like, a supporting plate bonded to a top surface of the semiconductor substrate to cover the pad electrode and a via hole formed in the semiconductor substrate and extending from a back surface of the semiconductor substrate to the pad electrode, wherein an aperture of the via hole at a portion close to the pad electrode is larger than an aperture of the via hole at a portion close to the back surface of the semiconductor substrate.

摘要翻译： 提供了可靠性提高的半导体器件及其制造方法。 本发明的半导体器件包括半导体衬底，通过由氧化硅，氮化硅等形成的绝缘层在半导体衬底上形成的焊盘电极，接合到半导体衬底的顶表面以覆盖衬垫的支撑板 电极和形成在半导体衬底中并从半导体衬底的背表面延伸到焊盘电极的通孔，其中靠近焊盘电极的部分处的通孔的孔径大于通孔的孔径 靠近半导体衬底的背面的部分。