Structure and method for fabricating heterojunction bipolar transistors and high electron mobility transistors utilizing the formation of a complaint substrates for materials used to form the same
    3.
    发明申请
    Structure and method for fabricating heterojunction bipolar transistors and high electron mobility transistors utilizing the formation of a complaint substrates for materials used to form the same 失效
    用于制造异质结双极晶体管和高电子迁移率晶体管的结构和方法,其利用形成用于形成异质结双极晶体管的材料的投诉基板

    公开(公告)号:US20030017683A1

    公开(公告)日:2003-01-23

    申请号:US09906783

    申请日:2001-07-18

    申请人: MOTOROLA, INC.

    IPC分类号: H01L021/20

    摘要: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. Once such a structure is built, a high electron mobility transistor (HEMT) or a heterojunction bipolar transistor (HBT) can be constructed on the structure. A HEMT or HBT of the above structure can then be used in a switch or in an amplifier.

    摘要翻译: 通过形成用于生长单晶层的柔性衬底,可以将单晶材料的高质量外延层生长在覆盖单晶衬底(例如大硅晶片)上。 容纳缓冲层包括通过硅氧化物的非晶界面层与硅晶片间隔开的单晶氧化物层。 非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。 容纳缓冲层与下面的硅晶片和上覆的单晶材料层晶格匹配。 通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。 一旦构建了这种结构,就可以在该结构上构建高电子迁移率晶体管(HEMT)或异质结双极晶体管(HBT)。 因此,上述结构的HEMT或HBT可用于开关或放大器中。

    Structure and method for fabricating semiconductor structures and devices with integrated control components
    5.
    发明申请
    Structure and method for fabricating semiconductor structures and devices with integrated control components 审中-公开
    用于制造具有集成控制元件的半导体结构和器件的结构和方法

    公开(公告)号:US20030015767A1

    公开(公告)日:2003-01-23

    申请号:US09905932

    申请日:2001-07-17

    申请人: MOTOROLA, INC.

    IPC分类号: H01L029/00

    摘要: Controlling and controlled components are integrated on a monolithic device. High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials. By providing both compound and Group IV semiconductor materials in one integrated circuit, both control and controlled components are integrated on one device.

    摘要翻译: 控制和受控组件集成在单片设备上。 通过形成用于生长单晶层的柔性衬底,可以将单晶材料的高质量外延层生长在覆盖单晶衬底(例如大硅晶片)上。 容纳缓冲层包括通过硅氧化物的非晶界面层与硅晶片间隔开的单晶氧化物层。 非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。 容纳缓冲层与下面的硅晶片和上覆的单晶材料层晶格匹配。 通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。 此外,顺应性衬底的形成可以包括利用表面活性剂增强的外延,将单晶硅外延生长到单晶氧化物上,以及Zintl相材料的外延生长。 通过在一个集成电路中提供化合物和第IV族半导体材料,控制和受控部件都集成在一个器件上。

    INTEGRATED IMPEDANCE MATCHING AND STABILITY NETWORK
    8.
    发明申请
    INTEGRATED IMPEDANCE MATCHING AND STABILITY NETWORK 失效
    集成阻抗匹配和稳定性网络

    公开(公告)号:US20030015730A1

    公开(公告)日:2003-01-23

    申请号:US09905903

    申请日:2001-07-17

    申请人: Motorola, Inc.

    IPC分类号: H01L031/0328 H01L029/00

    摘要: An integrated circuit for intermediate impedance matching and stabilization of high power devices is disclosed. High quality epitaxial layers of monocrystalline materials grown over monocrystalline substrates enables the formation of impedance matching and stability circuits to be placed on the same substrate as the active device. Additionally, by using the manifolds of the active to form plates of a capacitor, an impedance matching network of series inductance and shunt capacitor can be compactly fabricated for increasing the output impedance to intermediate levels. The manifolds of the active device are also used to form capacitors to provide stability to high power active devices.

    摘要翻译: 公开了一种用于大功率器件的中间阻抗匹配和稳定的集成电路。 在单晶衬底上生长的单晶材料的高质量外延层使得能够形成阻抗匹配和稳定性电路,以将其放置在与有源器件相同的衬底上。 此外,通过使用有源的歧管形成电容器的板,可以紧凑地制造串联电感和并联电容器的阻抗匹配网络,以将输出阻抗增加到中间电平。 有源器件的歧管也用于形成电容器以向高功率有源器件提供稳定性。

    Optically tuned transistor
    9.
    发明申请
    Optically tuned transistor 审中-公开
    光电调谐晶体管

    公开(公告)号:US20030007533A1

    公开(公告)日:2003-01-09

    申请号:US09899996

    申请日:2001-07-09

    申请人: MOTOROLA, INC.

    IPC分类号: H01S005/00

    摘要: An optically tuned transistor network is disclosed. High quality epitaxial layers of monocrystalline materials grown over monocrystalline substrates enables the formation of complementary metal oxide semiconductors along with light sources such as vertical cavity surface emitting lasers in one integrated circuit. By coupling the light source to active devices fabricated on the same substrate and coupling them with optical interconnects, light can be illuminated on the active regions of the active devices to tune various performance characteristics of the active device.

    摘要翻译: 公开了一种光调谐晶体管网络。 在单晶衬底上生长的单晶材料的高质量外延层使得能够在一个集成电路中形成互补金属氧化物半导体以及诸如垂直腔表面发射激光器的光源。 通过将光源耦合到在同一衬底上制造的有源器件并将其与光学互连件耦合,可以在有源器件的有源区上照亮光,以调节有源器件的各种性能特性。

    Semiconductor structure for spacial power combining and method of fabrication
    10.
    发明申请
    Semiconductor structure for spacial power combining and method of fabrication 审中-公开
    用于空间功率组合的半导体结构和制造方法

    公开(公告)号:US20020190270A1

    公开(公告)日:2002-12-19

    申请号:US09882062

    申请日:2001-06-18

    申请人: MOTOROLA, INC.

    发明人: Rudy M. Emrick

    IPC分类号: H01L029/04

    摘要: A semiconductor structure for spacial power combining includes a monocrystalline silicon substrate, an amorphous oxide material overlying the monocrystalline silicon substrate, a monocrystalline perovskite oxide material overlying the amorphous oxide material, a monocrystalline compound semiconductor material overlying the monocrystalline perovskite oxide material, a first amplifier in the monocrystalline compound semiconductor material, and a first control circuit in the monocrystalline silicon substrate and electrically coupled to the first amplifier.

    摘要翻译: 用于空间功率组合的半导体结构包括单晶硅衬底,覆盖单晶硅衬底的非晶氧化物材料,覆盖在非晶氧化物材料上的单晶钙钛矿氧化物材料,覆盖单晶钙钛矿氧化物材料的单晶化合物半导体材料,第一放大器 单晶化合物半导体材料,以及单晶硅衬底中的第一控制电路,并且电耦合到第一放大器。