公开(公告)号：US07829382B2

公开(公告)日：2010-11-09

申请号：US12699787

申请日：2010-02-03

申请人： Marcos Karnezos ,  Flynn Carson ,  Youngcheol Kim

发明人： Marcos Karnezos ,  Flynn Carson ,  Youngcheol Kim

IPC分类号： H01L21/00 ,  H01L23/02 ,  H05K5/00

CPC分类号： H01L25/03 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method for making a multipackage module that has multiple die of various types and having various functions and, in some embodiments, the module includes a digital processor, an analog device, and memory. A first die, having a comparatively large footprint, is mounted onto first die attach region on a surface of a first package substrate. A second die, having a significantly smaller footprint, is mounted upon the surface of the first die, on a second die attach region toward one edge of the first die. The first die is electrically connected by wire bonds to conductive traces in the die-attach side of the substrate. The second die is electrically connected by wire bonds to the first package substrate, and may additionally be electrically connected by wire bonds to the first die.

摘要翻译： 一种用于制造具有各种类型的多个管芯并具有各种功能的多包层模块的方法，并且在一些实施例中，该模块包括数字处理器，模拟设备和存储器。 具有相对较大占地面积的第一模具安装在第一封装衬底的表面上的第一裸片附着区域上。 具有明显更小的占地面积的第二模具安装在第一模具的表面上，朝向第一模具的一个边缘的第二芯片附接区域上。 第一裸片通过引线键合连接到衬底的芯片附接侧中的导电迹线。 第二管芯通过引线接合电连接到第一封装衬底，并且还可以通过引线电连接到第一管芯。

公开(公告)号：US07253511B2

公开(公告)日：2007-08-07

申请号：US11022375

申请日：2004-12-23

申请人： Marcos Karnezos ,  Flynn Carson ,  Youngcheol Kim

发明人： Marcos Karnezos ,  Flynn Carson ,  Youngcheol Kim

IPC分类号： H01L23/02 ,  H01L21/00 ,  H05K5/00

CPC分类号： H01L25/03 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A multipackage module has multiple die of various types and having various functions and, in some embodiments, the module includes a digital processor, an analog device, and memory. A first die, having a comparatively large footprint, is mounted onto first die attach region on a surface of a first package substrate. A second die, having a significantly smaller footprint, is mounted upon the surface of the first die, on a second die attach region toward one edge of the first die. The first die is electrically connected by wire bonds to conductive traces in the die-attach side of the substrate. The second die is electrically connected by wire bonds to the first package substrate, and may additionally be electrically connected by wire bonds to the first die. In some embodiments a spacer is mounted upon the first die, on a spacer attach region of the surface of the first die that is not within the die attach region, and which may be generally near a margin of the first die. A land grid array (LGA) package is inverted and mounted upon the spacer, with one margin of the LGA package near the edge of the spacer, so that much of the LGA package overhangs the second die. In other embodiments an additional spacer is mounted upon the first die, on a second spacer attach region that is not within the die attach region and not within the first spacer attach region, and the inverted LGA package is mounted upon both spacers. In still other embodiments a first spacer having a thickness approximating the thickness of the second die is mounted in a spacer attach region upon the first die; additional spacers are mounted upon both the first spacer and the second die, and the inverted LGA package is mounted upon the additional spacers. The LGA package is electrically connected to the first package substrate by wire bonds between bond sites on the LGA package and bond sites on the BGA package.

公开(公告)号：US20070278658A1

公开(公告)日：2007-12-06

申请号：US11772776

申请日：2007-07-02

申请人： Marcos Karnezos ,  Flynn Carson ,  Youngcheol Kim

发明人： Marcos Karnezos ,  Flynn Carson ,  Youngcheol Kim

IPC分类号： H01L23/12 ,  H01L21/58 ,  H01L23/48

CPC分类号： H01L25/03 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A multipackage module has multiple die of various types and having various functions and, in some embodiments, the module includes a digital processor, an analog device, and memory. A first die, having a comparatively large footprint, is mounted onto first die attach region on a surface of a first package substrate. A second die, having a significantly smaller footprint, is mounted upon the surface of the first die, on a second die attach region toward one edge of the first die. The first die is electrically connected by wire bonds to conductive traces in the die-attach side of the substrate. The second die is electrically connected by wire bonds to the first package substrate, and may additionally be electrically connected by wire bonds to the first die. In some embodiments a spacer is mounted upon the first die, on a spacer attach region of the surface of the first die that is not within the die attach region, and which may be generally near a margin of the first die. A land grid array (LGA) package is inverted and mounted upon the spacer, with one margin of the LGA package near the edge of the spacer, so that much of the LGA package overhangs the second die. In other embodiments an additional spacer is mounted upon the first die, on a second spacer attach region that is not within the die attach region and not within the first spacer attach region, and the inverted LGA package is mounted upon both spacers. In still other embodiments a first spacer having a thickness approximating the thickness of the second die is mounted in a spacer attach region upon the first die; additional spacers are mounted upon both the first spacer and the second die, and the inverted LGA package is mounted upon the additional spacers. The LGA package is electrically connected to the first package substrate by wire bonds between bond sites on the LGA package and bond sites on the BGA package.

公开(公告)号：US07692279B2

公开(公告)日：2010-04-06

申请号：US11772776

申请日：2007-07-02

申请人： Marcos Karnezos ,  Flynn Carson ,  Youngcheol Kim

发明人： Marcos Karnezos ,  Flynn Carson ,  Youngcheol Kim

IPC分类号： H01L23/02 ,  H01L21/00 ,  H05K5/00

CPC分类号： H01L25/03 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A multipackage module has multiple die of various types and having various functions and, in some embodiments, the module includes a digital processor, an analog device, and memory. A first die, having a comparatively large footprint, is mounted onto first die attach region on a surface of a first package substrate. A second die, having a significantly smaller footprint, is mounted upon the surface of the first die, on a second die attach region toward one edge of the first die. The first die is electrically connected by wire bonds to conductive traces in the die-attach side of the substrate. The second die is electrically connected by wire bonds to the first package substrate, and may additionally be electrically connected by wire bonds to the first die.

摘要翻译： 多包装模块具有各种类型的多个管芯并且具有各种功能，并且在一些实施例中，该模块包括数字处理器，模拟设备和存储器。 具有相对较大占地面积的第一模具安装在第一封装衬底的表面上的第一裸片附着区域上。 具有明显更小的占地面积的第二模具安装在第一模具的表面上，朝向第一模具的一个边缘的第二芯片附接区域上。 第一裸片通过引线键合连接到衬底的芯片附接侧中的导电迹线。 第二管芯通过引线接合电连接到第一封装衬底，并且还可以通过引线电连接到第一管芯。

公开(公告)号：US20060012018A1

公开(公告)日：2006-01-19

申请号：US11022375

申请日：2004-12-23

申请人： Marcos Karnezos ,  Flynn Carson ,  Youngcheol Kim

发明人： Marcos Karnezos ,  Flynn Carson ,  Youngcheol Kim

IPC分类号： H01L23/02

CPC分类号： H01L25/03 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A multipackage module has multiple die of various types and having various functions and, in some embodiments, the module includes a digital processor, an analog device, and memory. A first die, having a comparatively large footprint, is mounted onto first die attach region on a surface of a first package substrate. A second die, having a significantly smaller footprint, is mounted upon the surface of the first die, on a second die attach region toward one edge of the first die. The first die is electrically connected by wire bonds to conductive traces in the die-attach side of the substrate. The second die is electrically connected by wire bonds to the first package substrate, and may additionally be electrically connected by wire bonds to the first die. In some embodiments a spacer is mounted upon the first die, on a spacer attach region of the surface of the first die that is not within the die attach region, and which may be generally near a margin of the first die. A land grid array (LGA) package is inverted and mounted upon the spacer, with one margin of the LGA package near the edge of the spacer, so that much of the LGA package overhangs the second die. In other embodiments an additional spacer is mounted upon the first die, on a second spacer attach region that is not within the die attach region and not within the first spacer attach region, and the inverted LGA package is mounted upon both spacers. In still other embodiments a first spacer having a thickness approximating the thickness of the second die is mounted in a spacer attach region upon the first die; additional spacers are mounted upon both the first spacer and the second die, and the inverted LGA package is mounted upon the additional spacers. The LGA package is electrically connected to the first package substrate by wire bonds between bond sites on the LGA package and bond sites on the BGA package.

公开(公告)号：US20100136744A1

公开(公告)日：2010-06-03

申请号：US12699787

申请日：2010-02-03

申请人： Marcos Karnezos ,  Flynn Carson ,  Youngcheol Kim

发明人： Marcos Karnezos ,  Flynn Carson ,  Youngcheol Kim

IPC分类号： H01L21/50

CPC分类号： H01L25/03 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method for making a multipackage module that has multiple die of various types and having various functions and, in some embodiments, the module includes a digital processor, an analog device, and memory. A first die, having a comparatively large footprint, is mounted onto first die attach region on a surface of a first package substrate. A second die, having a significantly smaller footprint, is mounted upon the surface of the first die, on a second die attach region toward one edge of the first die. The first die is electrically connected by wire bonds to conductive traces in the die-attach side of the substrate. The second die is electrically connected by wire bonds to the first package substrate, and may additionally be electrically connected by wire bonds to the first die.

摘要翻译： 一种用于制造具有各种类型的多个管芯并具有各种功能的多包层模块的方法，并且在一些实施例中，该模块包括数字处理器，模拟设备和存储器。 具有相对较大占地面积的第一模具安装在第一封装衬底的表面上的第一裸片附着区域上。 具有明显更小的占地面积的第二模具安装在第一模具的表面上，朝向第一模具的一个边缘的第二芯片附接区域上。 第一裸片通过引线键合连接到衬底的芯片附接侧中的导电迹线。 第二管芯通过引线接合电连接到第一封装衬底，并且还可以通过引线电连接到第一管芯。

公开(公告)号：US08410594B2

公开(公告)日：2013-04-02

申请号：US11330930

申请日：2006-01-11

申请人： Kwang Soon Hwang ,  Youngcheol Kim ,  Hun Teak Lee ,  Koo Hong Lee

发明人： Kwang Soon Hwang ,  Youngcheol Kim ,  Hun Teak Lee ,  Koo Hong Lee

IPC分类号： H01L23/02

CPC分类号： H01L25/18 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19107 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： An inter-stacking module system is provided by mounting an integrated circuit on a first substrate, the first substrate having a first bond pad, mounting an inter-stacking module substrate over the integrated circuit, forming an inter-stacking module bonding pad on the inter-stacking module substrate, and connecting bond wires between the inter-stacking module bonding pad and the first bond pad.

摘要翻译： 通过将集成电路安装在第一基板上来提供堆叠间堆叠模块系统，第一基板具有第一接合焊盘，在集成电路上安装层间堆叠模块基板，在相互之间形成层间堆叠模块焊盘 - 堆叠模块基板，以及在堆叠间模块焊盘和第一焊盘之间的连接接合线。

公开(公告)号：US20100244245A1

公开(公告)日：2010-09-30

申请号：US12813335

申请日：2010-06-10

申请人： Rajendra D. Pendse ,  Youngcheol Kim ,  TaeKeun Lee ,  GuiChea Na ,  GwangJin Kim

发明人： Rajendra D. Pendse ,  Youngcheol Kim ,  TaeKeun Lee ,  GuiChea Na ,  GwangJin Kim

IPC分类号： H01L23/498

CPC分类号： H05K3/3452 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0332 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16013 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81411 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/30105 ,  H05K3/0005 ,  H05K3/3436 ,  H05K2201/0989 ,  H05K2201/10734 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2224/81805

摘要： A semiconductor package includes a semiconductor die with a plurality of solder bumps formed on bump pads. A substrate has a plurality of contact pads each with an exposed sidewall. A solder resist is disposed opening over at least a portion of each contact pad. The solder bumps are reflowed to metallurgically and electrically connect to the contact pads. Each contact pad is sized according to a design rule defined by SRO+2*SRR−2X, where SRO is the solder resist opening, SRR is a solder registration for the manufacturing process, and X is a function of a thickness of the exposed sidewall of the contact pad. The value of X ranges from 5 to 20 microns. The solder bump wets the exposed sidewall of the contact pad and substantially fills an area adjacent to the exposed sidewall. The contact pad can be made circular, rectangular, or donut-shaped.

摘要翻译： 半导体封装包括具有形成在凸块焊盘上的多个焊料凸块的半导体管芯。 衬底具有多个具有暴露侧壁的接触焊盘。 阻焊剂设置在每个接触垫的至少一部分上方开口。 焊料凸块被回流到冶金和电连接到接触焊盘。 每个接触垫的大小根据由SRO + 2 * SRR-2X定义的设计规则，其中SRO是阻焊剂开口，SRR是制造工艺的焊料对准，X是暴露侧壁的厚度的函数 的接触垫。 X的值范围为5至20微米。 焊料凸块润湿接触焊盘的暴露的侧壁并且基本上填充与暴露的侧壁相邻的区域。 接触垫可以制成圆形，矩形或圆环状。

公开(公告)号：US20090243080A1

公开(公告)日：2009-10-01

申请号：US12055152

申请日：2008-03-25

申请人： Rajendra D. Pendse ,  Youngcheol Kim ,  TaeKeun Lee ,  GuiChea Na ,  GwangJin Kim

发明人： Rajendra D. Pendse ,  Youngcheol Kim ,  TaeKeun Lee ,  GuiChea Na ,  GwangJin Kim

IPC分类号： H01L23/488 ,  H01L21/60

CPC分类号： H05K3/3452 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0332 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16013 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81411 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/30105 ,  H05K3/0005 ,  H05K3/3436 ,  H05K2201/0989 ,  H05K2201/10734 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2224/81805

摘要： A semiconductor package includes a semiconductor die with a plurality of solder bumps formed on bump pads. A substrate has a plurality of contact pads each with an exposed sidewall. A solder resist is disposed opening over at least a portion of each contact pad. The solder bumps are reflowed to metallurgically and electrically connect to the contact pads. Each contact pad is sized according to a design rule defined by SRO+2*SRR−2X, where SRO is the solder resist opening, SRR is a solder registration for the manufacturing process, and X is a function of a thickness of the exposed sidewall of the contact pad. The value of X ranges from 5 to 20 microns. The solder bump wets the exposed sidewall of the contact pad and substantially fills an area adjacent to the exposed sidewall. The contact pad can be made circular, rectangular, or donut-shaped.

摘要翻译： 半导体封装包括具有形成在凸块焊盘上的多个焊料凸块的半导体管芯。 衬底具有多个具有暴露侧壁的接触焊盘。 阻焊剂设置在每个接触垫的至少一部分上方开口。 焊料凸块被回流到冶金和电连接到接触焊盘。 每个接触垫的大小根据由SRO + 2 * SRR-2X定义的设计规则，其中SRO是阻焊剂开口，SRR是制造工艺的焊料对准，X是暴露侧壁的厚度的函数 的接触垫。 X的值范围为5至20微米。 焊料凸块润湿接触焊盘的暴露的侧壁并且基本上填充与暴露的侧壁相邻的区域。 接触垫可以制成圆形，矩形或圆环状。

公开(公告)号：US20070158858A1

公开(公告)日：2007-07-12

申请号：US11330930

申请日：2006-01-11

申请人： Kwang Hwang ,  Youngcheol Kim ,  Hun Lee ,  Koo Lee

发明人： Kwang Hwang ,  Youngcheol Kim ,  Hun Lee ,  Koo Lee

IPC分类号： H01L23/52

CPC分类号： H01L25/18 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19107 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： An inter-stacking module system is provided by mounting an integrated circuit on a first substrate, the first substrate having a first bond pad, mounting an inter-stacking module substrate over the integrated circuit, forming an inter-stacking module bonding pad on the inter-stacking module substrate, and connecting bond wires between the inter-stacking module bonding pad and the first bond pad.

摘要翻译： 通过将集成电路安装在第一基板上来提供堆叠间堆叠模块系统，第一基板具有第一接合焊盘，在集成电路上安装层间堆叠模块基板，在相互之间形成层间堆叠模块焊盘 - 堆叠模块基板，以及在堆叠间模块焊盘和第一焊盘之间的连接接合线。