公开(公告)号：US20070278658A1

公开(公告)日：2007-12-06

申请号：US11772776

申请日：2007-07-02

申请人： Marcos Karnezos ,  Flynn Carson ,  Youngcheol Kim

发明人： Marcos Karnezos ,  Flynn Carson ,  Youngcheol Kim

IPC分类号： H01L23/12 ,  H01L21/58 ,  H01L23/48

CPC分类号： H01L25/03 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A multipackage module has multiple die of various types and having various functions and, in some embodiments, the module includes a digital processor, an analog device, and memory. A first die, having a comparatively large footprint, is mounted onto first die attach region on a surface of a first package substrate. A second die, having a significantly smaller footprint, is mounted upon the surface of the first die, on a second die attach region toward one edge of the first die. The first die is electrically connected by wire bonds to conductive traces in the die-attach side of the substrate. The second die is electrically connected by wire bonds to the first package substrate, and may additionally be electrically connected by wire bonds to the first die. In some embodiments a spacer is mounted upon the first die, on a spacer attach region of the surface of the first die that is not within the die attach region, and which may be generally near a margin of the first die. A land grid array (LGA) package is inverted and mounted upon the spacer, with one margin of the LGA package near the edge of the spacer, so that much of the LGA package overhangs the second die. In other embodiments an additional spacer is mounted upon the first die, on a second spacer attach region that is not within the die attach region and not within the first spacer attach region, and the inverted LGA package is mounted upon both spacers. In still other embodiments a first spacer having a thickness approximating the thickness of the second die is mounted in a spacer attach region upon the first die; additional spacers are mounted upon both the first spacer and the second die, and the inverted LGA package is mounted upon the additional spacers. The LGA package is electrically connected to the first package substrate by wire bonds between bond sites on the LGA package and bond sites on the BGA package.

公开(公告)号：US07829382B2

公开(公告)日：2010-11-09

申请号：US12699787

申请日：2010-02-03

申请人： Marcos Karnezos ,  Flynn Carson ,  Youngcheol Kim

发明人： Marcos Karnezos ,  Flynn Carson ,  Youngcheol Kim

IPC分类号： H01L21/00 ,  H01L23/02 ,  H05K5/00

CPC分类号： H01L25/03 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method for making a multipackage module that has multiple die of various types and having various functions and, in some embodiments, the module includes a digital processor, an analog device, and memory. A first die, having a comparatively large footprint, is mounted onto first die attach region on a surface of a first package substrate. A second die, having a significantly smaller footprint, is mounted upon the surface of the first die, on a second die attach region toward one edge of the first die. The first die is electrically connected by wire bonds to conductive traces in the die-attach side of the substrate. The second die is electrically connected by wire bonds to the first package substrate, and may additionally be electrically connected by wire bonds to the first die.

摘要翻译： 一种用于制造具有各种类型的多个管芯并具有各种功能的多包层模块的方法，并且在一些实施例中，该模块包括数字处理器，模拟设备和存储器。 具有相对较大占地面积的第一模具安装在第一封装衬底的表面上的第一裸片附着区域上。 具有明显更小的占地面积的第二模具安装在第一模具的表面上，朝向第一模具的一个边缘的第二芯片附接区域上。 第一裸片通过引线键合连接到衬底的芯片附接侧中的导电迹线。 第二管芯通过引线接合电连接到第一封装衬底，并且还可以通过引线电连接到第一管芯。

公开(公告)号：US07253511B2

公开(公告)日：2007-08-07

申请号：US11022375

申请日：2004-12-23

申请人： Marcos Karnezos ,  Flynn Carson ,  Youngcheol Kim

发明人： Marcos Karnezos ,  Flynn Carson ,  Youngcheol Kim

IPC分类号： H01L23/02 ,  H01L21/00 ,  H05K5/00

CPC分类号： H01L25/03 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A multipackage module has multiple die of various types and having various functions and, in some embodiments, the module includes a digital processor, an analog device, and memory. A first die, having a comparatively large footprint, is mounted onto first die attach region on a surface of a first package substrate. A second die, having a significantly smaller footprint, is mounted upon the surface of the first die, on a second die attach region toward one edge of the first die. The first die is electrically connected by wire bonds to conductive traces in the die-attach side of the substrate. The second die is electrically connected by wire bonds to the first package substrate, and may additionally be electrically connected by wire bonds to the first die. In some embodiments a spacer is mounted upon the first die, on a spacer attach region of the surface of the first die that is not within the die attach region, and which may be generally near a margin of the first die. A land grid array (LGA) package is inverted and mounted upon the spacer, with one margin of the LGA package near the edge of the spacer, so that much of the LGA package overhangs the second die. In other embodiments an additional spacer is mounted upon the first die, on a second spacer attach region that is not within the die attach region and not within the first spacer attach region, and the inverted LGA package is mounted upon both spacers. In still other embodiments a first spacer having a thickness approximating the thickness of the second die is mounted in a spacer attach region upon the first die; additional spacers are mounted upon both the first spacer and the second die, and the inverted LGA package is mounted upon the additional spacers. The LGA package is electrically connected to the first package substrate by wire bonds between bond sites on the LGA package and bond sites on the BGA package.

公开(公告)号：US20100136744A1

公开(公告)日：2010-06-03

申请号：US12699787

申请日：2010-02-03

申请人： Marcos Karnezos ,  Flynn Carson ,  Youngcheol Kim

发明人： Marcos Karnezos ,  Flynn Carson ,  Youngcheol Kim

IPC分类号： H01L21/50

CPC分类号： H01L25/03 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method for making a multipackage module that has multiple die of various types and having various functions and, in some embodiments, the module includes a digital processor, an analog device, and memory. A first die, having a comparatively large footprint, is mounted onto first die attach region on a surface of a first package substrate. A second die, having a significantly smaller footprint, is mounted upon the surface of the first die, on a second die attach region toward one edge of the first die. The first die is electrically connected by wire bonds to conductive traces in the die-attach side of the substrate. The second die is electrically connected by wire bonds to the first package substrate, and may additionally be electrically connected by wire bonds to the first die.

摘要翻译： 一种用于制造具有各种类型的多个管芯并具有各种功能的多包层模块的方法，并且在一些实施例中，该模块包括数字处理器，模拟设备和存储器。 具有相对较大占地面积的第一模具安装在第一封装衬底的表面上的第一裸片附着区域上。 具有明显更小的占地面积的第二模具安装在第一模具的表面上，朝向第一模具的一个边缘的第二芯片附接区域上。 第一裸片通过引线键合连接到衬底的芯片附接侧中的导电迹线。 第二管芯通过引线接合电连接到第一封装衬底，并且还可以通过引线电连接到第一管芯。

公开(公告)号：US07692279B2

公开(公告)日：2010-04-06

申请号：US11772776

申请日：2007-07-02

申请人： Marcos Karnezos ,  Flynn Carson ,  Youngcheol Kim

发明人： Marcos Karnezos ,  Flynn Carson ,  Youngcheol Kim

IPC分类号： H01L23/02 ,  H01L21/00 ,  H05K5/00

CPC分类号： H01L25/03 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A multipackage module has multiple die of various types and having various functions and, in some embodiments, the module includes a digital processor, an analog device, and memory. A first die, having a comparatively large footprint, is mounted onto first die attach region on a surface of a first package substrate. A second die, having a significantly smaller footprint, is mounted upon the surface of the first die, on a second die attach region toward one edge of the first die. The first die is electrically connected by wire bonds to conductive traces in the die-attach side of the substrate. The second die is electrically connected by wire bonds to the first package substrate, and may additionally be electrically connected by wire bonds to the first die.

摘要翻译： 多包装模块具有各种类型的多个管芯并且具有各种功能，并且在一些实施例中，该模块包括数字处理器，模拟设备和存储器。 具有相对较大占地面积的第一模具安装在第一封装衬底的表面上的第一裸片附着区域上。 具有明显更小的占地面积的第二模具安装在第一模具的表面上，朝向第一模具的一个边缘的第二芯片附接区域上。 第一裸片通过引线键合连接到衬底的芯片附接侧中的导电迹线。 第二管芯通过引线接合电连接到第一封装衬底，并且还可以通过引线电连接到第一管芯。

公开(公告)号：US20060012018A1

公开(公告)日：2006-01-19

申请号：US11022375

申请日：2004-12-23

申请人： Marcos Karnezos ,  Flynn Carson ,  Youngcheol Kim

发明人： Marcos Karnezos ,  Flynn Carson ,  Youngcheol Kim

IPC分类号： H01L23/02

CPC分类号： H01L25/03 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A multipackage module has multiple die of various types and having various functions and, in some embodiments, the module includes a digital processor, an analog device, and memory. A first die, having a comparatively large footprint, is mounted onto first die attach region on a surface of a first package substrate. A second die, having a significantly smaller footprint, is mounted upon the surface of the first die, on a second die attach region toward one edge of the first die. The first die is electrically connected by wire bonds to conductive traces in the die-attach side of the substrate. The second die is electrically connected by wire bonds to the first package substrate, and may additionally be electrically connected by wire bonds to the first die. In some embodiments a spacer is mounted upon the first die, on a spacer attach region of the surface of the first die that is not within the die attach region, and which may be generally near a margin of the first die. A land grid array (LGA) package is inverted and mounted upon the spacer, with one margin of the LGA package near the edge of the spacer, so that much of the LGA package overhangs the second die. In other embodiments an additional spacer is mounted upon the first die, on a second spacer attach region that is not within the die attach region and not within the first spacer attach region, and the inverted LGA package is mounted upon both spacers. In still other embodiments a first spacer having a thickness approximating the thickness of the second die is mounted in a spacer attach region upon the first die; additional spacers are mounted upon both the first spacer and the second die, and the inverted LGA package is mounted upon the additional spacers. The LGA package is electrically connected to the first package substrate by wire bonds between bond sites on the LGA package and bond sites on the BGA package.

公开(公告)号：US07429786B2

公开(公告)日：2008-09-30

申请号：US11394635

申请日：2006-03-31

申请人： Marcos Karnezos ,  Flynn Carson

发明人： Marcos Karnezos ,  Flynn Carson

IPC分类号： H01L23/02 ,  H05K1/18

CPC分类号： H01L25/0657 ,  H01L23/552 ,  H01L24/73 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/05553 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06558 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/06575 ,  H01L2225/06586 ,  H01L2225/06596 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor package subassembly includes a die affixed to, and electrically interconnected with, a die attach side of a first package substrate, and a second substrate having a first side and a second (“land”) side, mounted over the first package with the first side of the second substrate facing the die attach side of the first package substrate, and supported by a spacer or a spacer assembly. Z-interconnection of the package and the substrate is by wire bonds connecting the first and second substrates. The assembly is encapsulated in such a way that both the land side of the second substrate (one side of the assembly) and a portion of the land side of the first package substrate (on the opposite side of the assembly) are exposed, so that second level interconnection and interconnection with additional components may be made.

摘要翻译： 半导体封装子组件包括固定到第一封装衬底的管芯附接侧并与之电互连的管芯，以及具有安装在第一封装上的第一侧和第二（“焊盘”）侧的第二衬底， 第二基板的第一面朝向第一封装基板的管芯附接侧，并由间隔件或间隔件组件支撑。 封装和基板的Z形互连是通过连接第一和第二基板的引线键合。 该组件以这样一种方式封装，使得第二基板的接地侧（组件的一侧）和第一封装基板的陆部侧的一部分（在组件的相对侧）被露出，使得 可以进行二级互连和与附加组件的互连。

公开(公告)号：US07247519B2

公开(公告)日：2007-07-24

申请号：US11337944

申请日：2006-01-23

申请人： Marcos Karnezos ,  Flynn Carson

发明人： Marcos Karnezos ,  Flynn Carson

IPC分类号： H01L21/00 ,  H01L23/02

CPC分类号： H01L25/03 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/5385 ,  H01L23/552 ,  H01L24/16 ,  H01L24/29 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/162 ,  H01L25/50 ,  H01L2224/056 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/48247 ,  H01L2224/4846 ,  H01L2224/48465 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/854 ,  H01L2224/85424 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2225/06575 ,  H01L2225/06589 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/1532 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/19104 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/0665 ,  H01L2224/16225 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755

摘要： A semiconductor multi-package module has stacked lower and upper packages, each of which includes a die attached to a substrate, in which the second package is inverted, in which the upper and lower substrates are interconnected by wire bonding, and in which the inverted second package comprises a bump chip carrier package. Also, a method for making a semiconductor multi-package module, by providing a lower molded package including a lower substrate and a die, affixing an upper bump chip carrier package including an upper substrate in inverted orientation onto the upper surface of the lower package, and forming z-interconnects between the upper and lower substrates.

摘要翻译： 半导体多封装模块具有堆叠的下封装和上封装，每个封装包括附接到基板的管芯，其中第二封装反相，其中上基板和下基板通过引线接合互连，并且其中倒置 第二封装包括凸块芯片载体封装。 另外，制造半导体多封装模块的方法通过提供包括下基板和芯片的下模塑封装，将包括反向取向的上基板的上凸块芯片载体封装固定在下封装的上表面上， 以及在上基板和下基板之间形成z-互连。

公开(公告)号：US20060019429A1

公开(公告)日：2006-01-26

申请号：US11213058

申请日：2005-08-26

申请人： Taekeun Lee ,  Flynn Carson ,  Marcos Karnezos

发明人： Taekeun Lee ,  Flynn Carson ,  Marcos Karnezos

IPC分类号： H01L21/50

CPC分类号： H01L21/565 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/4334 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： A plastic ball grid array semiconductor package employs a metal heat spreader having supporting arms embedded in the molding cap, in which the embedded supporting arms are not directly affixed to the substrate or in which any supporting arm that is affixed to the substrate is affixed using a resilient material such as an elastomeric adhesive. Also, a process for forming the package includes steps of placing the heat spreader in a mold cavity, placing the substrate over the mold cavity such that the die support surface of the substrate contacts the supporting arms of the heat spreader, and injecting the molding material into the cavity to form the molding cap. The substrate is positioned in register over the mold cavity such that as the molding material hardens to form the mold cap the embedded heat spreader becomes fixed in the appropriate position in relation to the substrate. Also, a process for forming the package includes steps of placing the heat spreader onto the substrate such that at least one of the supporting arms of the heat spreader is affixed to the substrate using a resilient fixative such as an elastomeric adhesive, placing a mold cavity over the heat spreader, and injecting the molding material into the cavity. The elastomeric adhesive holds the heat spreader in the appropriate position in relation to the substrate during injection of the molding material, and as the molding material hardens to form the mold cap the embedded heat spreader becomes fixed in the appropriate position in relation to the substrate. In some embodiments the under surface of the heat spreader at the interface between the heat spreader and the molding compound is roughened, or includes a black copper oxide layer, to improve adhesion and contact between the heat spreader and the molding material. The invention can provide significant improvements in manufacturability and reliability in use.

摘要翻译： 塑料球栅阵列半导体封装采用金属散热器，其具有嵌入在成型帽中的支撑臂，其中嵌入的支撑臂不直接固定到基板上，或者使用附接到基板的任何支撑臂 弹性粘合剂如弹性材料。 此外，用于形成包装的方法包括以下步骤：将散热器放置在模腔中，将基板放置在模腔上，使得基板的模具支撑表面接触散热器的支撑臂，并且将模制材料 进入模腔以形成模制帽。 基板被定位在模腔上，使得当模制材料硬化以形成模具盖时，嵌入式散热器相对于基板固定在适当的位置。 而且，用于形成包装的方法包括以下步骤：将散热器放置在基板上，使得散热器的至少一个支撑臂使用诸如弹性体粘合剂的弹性固定剂固定到基板上，放置模具腔 在散热器上方，并将成型材料注入空腔。 弹性粘合剂在注射成型材料期间将散热器相对于基板保持在适当的位置，并且当模制材料硬化以形成模具盖时，嵌入的散热器相对于基板固定在适当的位置。 在一些实施例中，散热器在散热器和模塑料之间的界面处的下表面被粗糙化，或包括黑色氧化铜层，以改善散热器与成型材料之间的粘附和接触。 本发明可以在可制造性和使用可靠性方面提供显着的改进。

公开(公告)号：US07494847B2

公开(公告)日：2009-02-24

申请号：US11880893

申请日：2007-07-23

申请人： Marcos Karnezos ,  Flynn Carson

发明人： Marcos Karnezos ,  Flynn Carson

IPC分类号： H01L21/00 ,  H01L23/02

CPC分类号： H01L23/3128 ,  H01L21/563 ,  H01L23/3135 ,  H01L23/4334 ,  H01L23/552 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor multi-package module has stacked lower and upper packages, each of which includes a die attached to a substrate, in which the second package is inverted, in which the upper and lower substrates are interconnected by wire bonding, and in which the inverted second package comprises a wire bond carrier package. Also, a method for making a semiconductor multi-package module, by providing a lower molded package including a lower substrate and a die, affixing an upper wire bond carrier package including an upper substrate in inverted orientation onto the upper surface of the lower package, and forming z-interconnects between the upper and lower substrates.

摘要翻译： 半导体多封装模块具有堆叠的下封装和上封装，每个封装包括附接到基板的管芯，其中第二封装反相，其中上基板和下基板通过引线接合互连，并且其中倒置 第二包装包括引线键合载体封装。 另外，制造半导体多封装模块的方法通过提供包括下基板和芯片的下模塑封装，将包括反向取向的上基板的上引线键合载体封装固定在下封装的上表面上， 以及在上基板和下基板之间形成z-互连。