公开(公告)号：US20140054783A1

公开(公告)日：2014-02-27

申请号：US13591924

申请日：2012-08-22

申请人： ZHIWEI GONG (Tony) ,  Michael B. Vincent ,  Scott M. Hayes ,  Jason R. Wright

发明人： ZHIWEI GONG (Tony) ,  Michael B. Vincent ,  Scott M. Hayes ,  Jason R. Wright

IPC分类号： H01L23/48 ,  H01L21/50

CPC分类号： H01L25/065 ,  H01L24/19 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： Methods for fabricating stacked microelectronic packages are provided, as are embodiments of a stacked microelectronic package. In one embodiment, the method includes arranging a plurality of microelectronic device panels in a panel stack. Each microelectronic device panel contains plurality of microelectronic devices and a plurality of package edge conductors extending therefrom. Trenches are created in the panel stack exposing the plurality of package edge conductors, and a plurality of sidewall conductors is formed interconnecting different ones of the package edge conductors exposed through the trenches. The panel stack is then separated into a plurality of stacked microelectronic packages each including at least two microelectronic devices electrically interconnected by at least one of the plurality of sidewall conductors included within the stacked microelectronic package.

摘要翻译： 提供了堆叠的微电子封装的制造方法，如堆叠的微电子封装的实施例。 在一个实施例中，该方法包括在面板堆叠中布置多个微电子器件面板。 每个微电子器件面板包含多个微电子器件和从其延伸的多个封装边缘导体。 在面板堆叠中产生暴露多个封装边缘导体的沟槽，并且形成多个侧壁导体，其互连通过沟槽暴露的不同封装边缘导体。 面板堆叠然后被分离成多个层叠的微电子封装，每个包含至少两个微电子器件，所述至少两个微电子器件由堆叠的微电子封装内的多个侧壁导体中的至少一个电气互连。

公开(公告)号：US09502363B2

公开(公告)日：2016-11-22

申请号：US14223805

申请日：2014-03-24

申请人： Michael B. Vincent ,  Trung Q. Duong ,  Zhiwei Gong ,  Scott M. Hayes ,  Alan J. Magnus ,  Douglas G. Mitchell ,  Eduard J. Pabst ,  Jason R. Wright ,  Weng F. Yap

发明人： Michael B. Vincent ,  Trung Q. Duong ,  Zhiwei Gong ,  Scott M. Hayes ,  Alan J. Magnus ,  Douglas G. Mitchell ,  Eduard J. Pabst ,  Jason R. Wright ,  Weng F. Yap

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC分类号： H01L24/02 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/564 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/96 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2924/014

摘要： Wafer level packages and methods for producing wafer level packages having delamination-resistant redistribution layers are provided. In one embodiment, the method includes building inner redistribution layers over a semiconductor die. Inner redistribution layers include a body of dielectric material containing metal routing features. A routing-free dielectric block is formed in the body of dielectric material and is uninterrupted by the metal routing features. An outer redistribution layer is produced over the inner redistribution layers and contains a metal plane, which is patterned to include one or more outgassing openings overlying the routing-free dielectric block. The routing-free dielectric block has a minimum width, length, and depth each at least twice the thickness of the outer redistribution layer.

摘要翻译： 提供了晶片级封装以及用于生产具有防分层再分配层的晶片级封装的方法。 在一个实施例中，该方法包括在半导体管芯上建立内部再分布层。 内部再分布层包括含有金属布线特征的绝缘材料体。 在电介质材料的主体中形成无路由的介质块，并且不被金属布线特征中断。 外再分布层在内再分布层上产生并且包含金属平面，其被图案化以包括覆盖无路由介质块的一个或多个除气开口。 无路由介质块具有最小宽度，长度和深度，每个至少两倍于外再分布层的厚度。

公开(公告)号：US09281293B2

公开(公告)日：2016-03-08

申请号：US14067809

申请日：2013-10-30

申请人： Alan J. Magnus ,  Trung Q. Duong ,  Zhiwei Gong ,  Scott M. Hayes ,  Douglas G. Mitchell ,  Michael B. Vincent ,  Jason R. Wright ,  Weng F. Yap

发明人： Alan J. Magnus ,  Trung Q. Duong ,  Zhiwei Gong ,  Scott M. Hayes ,  Douglas G. Mitchell ,  Michael B. Vincent ,  Jason R. Wright ,  Weng F. Yap

IPC分类号： H01L23/00 ,  H01L21/56

CPC分类号： H01L24/97 ,  H01L21/568 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/19

摘要： Microelectronic packages having layered interconnect structures are provided, as are methods for the fabrication thereof. In one embodiment, the method includes forming a first plurality of interconnect lines in ohmic contact with a first bond pad row provided on a semiconductor. A dielectric layer is deposited over the first plurality of interconnect lines, the first bond pad row, and a second bond pad row adjacent the first bond pad row. A trench via is then formed in the dielectric layer to expose at least the second bond pad row therethrough. A second plurality of interconnect lines is formed in ohmic contact with the second bond pad row within the trench via. The second plurality of interconnect lines extends over the first bond pad row and is electrically isolated therefrom by the dielectric layer to produce at least a portion of the layered interconnect structure.

摘要翻译： 提供具有分层互连结构的微电子封装，以及制造它们的方法。 在一个实施例中，该方法包括形成与设置在半导体上的第一接合焊盘排欧姆接触的第一多个互连线。 介电层沉积在第一多个互连线上，第一接合焊盘行和与第一接合焊盘行相邻的第二接合焊盘排。 然后在电介质层中形成沟槽通孔，以至少暴露第二接合焊盘排。 第二多个互连线形成为与沟槽通孔内的第二接合焊盘排欧姆接触。 所述第二多个互连线延伸穿过所述第一接合焊盘行并且通过所述电介质层与其电隔离以产生所述分层互连结构的至少一部分。

公开(公告)号：US20140054797A1

公开(公告)日：2014-02-27

申请号：US13591990

申请日：2012-08-22

申请人： Zhiwei Gong (Tony) ,  Michael B. Vincent ,  Scott M. Hayes ,  Jason R. Wright

发明人： Zhiwei Gong (Tony) ,  Michael B. Vincent ,  Scott M. Hayes ,  Jason R. Wright

IPC分类号： H01L23/48 ,  H01L21/50 ,  H01L21/78

CPC分类号： H01L25/0657 ,  H01L21/4853 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49805 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L25/03 ,  H01L25/105 ,  H01L25/50 ,  H01L2225/06551 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/00

摘要： Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of stacked microelectronic packages. In one embodiment, the method includes producing a partially-completed stacked microelectronic package including a package body having a vertical package sidewall, a plurality microelectronic devices embedded within the package body, and package edge conductors electrically coupled to the plurality of microelectronic devices and extending to the vertical package sidewall. A flowable conductive material is applied on the vertical package sidewall and contacts the package edge conductors. Selected portions of the flowable conductive material are then removed to define, at least in part, electrically-isolated sidewall conductors electrically coupled to different ones of the package edge conductors.

摘要翻译： 提供了用于制造堆叠的微电子封装的方法的实施例，如堆叠的微电子封装的实施例。 在一个实施例中，该方法包括产生部分完成的叠层微电子封装，其包括具有垂直封装侧壁的封装体，嵌入封装主体内的多个微电子器件，以及电耦合到多个微电子器件的封装边缘导体， 垂直封装侧壁。 可流动的导电材料施加在垂直封装侧壁上，并与封装边缘导体接触。 然后去除可流动导电材料的选定部分，以至少部分地限定电隔离的侧壁导体，其电耦合到不同的封装边缘导体。

公开(公告)号：US20140054796A1

公开(公告)日：2014-02-27

申请号：US13591969

申请日：2012-08-22

申请人： Zhiwei (Tony) Gong ,  Michael B. Vincent ,  Scott M. Hayes ,  Jason R. Wright

发明人： Zhiwei (Tony) Gong ,  Michael B. Vincent ,  Scott M. Hayes ,  Jason R. Wright

IPC分类号： H01L23/48 ,  H01L21/28 ,  H01L21/78 ,  H01L21/56

CPC分类号： H01L23/5389 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/49805 ,  H01L23/49838 ,  H01L24/24 ,  H01L24/48 ,  H01L24/82 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/24145 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

摘要： Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of a stacked microelectronic package. In one embodiment, the method includes arranging microelectronic device panels in a panel stack. Each microelectronic device panel includes a plurality of microelectronic devices and a plurality of package edge conductors extending therefrom. Trenches are formed in the panel stack exposing the plurality of package edge conductors. An electrically-conductive material is deposited into the trenches and contacts the plurality of package edge conductors exposed therethrough. The panel stack is then separated into partially-completed stacked microelectronic packages. For at least one of the partially-completed stacked microelectronic packages, selected portions of the electrically-conductive material are removed to define a plurality of patterned sidewall conductors interconnecting the microelectronic devices included within the stacked microelectronic package.

摘要翻译： 提供了用于制造堆叠的微电子封装的方法的实施例，如堆叠微电子封装的实施例。 在一个实施例中，该方法包括将微电子器件面板布置在面板堆叠中。 每个微电子器件面板包括多个微电子器件和从其延伸的多个封装边缘导体。 沟槽形成在面板堆叠中，暴露多个封装边缘导体。 导电材料沉积到沟槽中并接触暴露于其中的多个封装边缘导体。 然后将面板堆叠分成部分完成的堆叠微电子封装。 对于部分完成的叠层微电子封装中的至少一个，移除导电材料的选定部分以限定互连包含在堆叠的微电子封装内的微电子器件的多个图案化侧壁导体。

公开(公告)号：US09673150B2

公开(公告)日：2017-06-06

申请号：US14571878

申请日：2014-12-16

申请人： Zhiwei Gong ,  Scott M. Hayes ,  Michael B. Vincent

发明人： Zhiwei Gong ,  Scott M. Hayes ,  Michael B. Vincent

IPC分类号： H01L23/34 ,  H01L23/552 ,  H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L21/3205 ,  H01L23/00 ,  H01L23/498

CPC分类号： H01L23/552 ,  H01L21/3205 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49827 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05554 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/10161 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/207 ,  H01L2924/3025 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015

摘要： An encapsulated semiconductor device package with an overlying conductive EMI or RFI shield in contact with an end of a grounded conductive component at a lateral side of the package, and methods of making the semiconductor device package.

公开(公告)号：US09595485B2

公开(公告)日：2017-03-14

申请号：US14316580

申请日：2014-06-26

申请人： Michael B. Vincent ,  Scott M. Hayes

发明人： Michael B. Vincent ,  Scott M. Hayes

IPC分类号： H01L23/31 ,  H01L23/00 ,  H01L25/10 ,  H01L21/56 ,  H01L23/538 ,  H01L25/00 ,  H01L23/498 ,  H01L21/78

CPC分类号： H01L25/0657 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/528 ,  H01L23/5389 ,  H01L24/09 ,  H01L24/19 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/0237 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06551 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2924/35

摘要： Methods for fabricating microelectronic packages and microelectronic packages are provided. In one embodiment, the microelectronic package fabrication method includes producing a molded panel containing a sidewall substrate. The molded panel is singulated to produce a Fan-Out Wafer Level Package core including a molded body having a fan-out region in which the sidewall substrate is embedded. A side connect trace is printed or otherwise formed on a sidewall of the Fan-Out Wafer Level Package core and extends at least partially across the embedded sidewall substrate.

摘要翻译： 提供了制造微电子封装和微电子封装的方法。 在一个实施例中，微电子封装制造方法包括制造包含侧壁基板的模制板。 将模制板分割成产生扇出晶片级封装芯，该芯包括具有嵌入侧壁基板的扇出区域的成型体。 侧面连接迹线印刷或以其它方式形成在扇出晶片级封装芯的侧壁上，并且至少部分地延伸穿过嵌入的侧壁基板。

公开(公告)号：US20160172309A1

公开(公告)日：2016-06-16

申请号：US14571878

申请日：2014-12-16

申请人： Zhiwei Gong ,  Scott M. Hayes ,  Michael B. Vincent

发明人： Zhiwei Gong ,  Scott M. Hayes ,  Michael B. Vincent

IPC分类号： H01L23/552 ,  H01L23/00 ,  H01L21/3205 ,  H01L21/56 ,  H01L21/78 ,  H01L23/495 ,  H01L23/31

CPC分类号： H01L23/552 ,  H01L21/3205 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49827 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05554 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/10161 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/207 ,  H01L2924/3025 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015

摘要： An encapsulated semiconductor device package with an overlying conductive EMI or RFI shield in contact with an end of a grounded conductive component at a lateral side of the package, and methods of making the semiconductor device package.

摘要翻译： 一种封装的半导体器件封装，其具有与封装的侧面处的接地导电部件的端部接触的上覆导电EMI或RFI屏蔽以及制造半导体器件封装的方法。

公开(公告)号：US09263420B2

公开(公告)日：2016-02-16

申请号：US14097424

申请日：2013-12-05

申请人： Michael B. Vincent ,  Scott M. Hayes

发明人： Michael B. Vincent ,  Scott M. Hayes

IPC分类号： H01L25/065 ,  H01L25/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

CPC分类号： H01L25/0657 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/528 ,  H01L23/53204 ,  H01L23/5328 ,  H01L23/5329 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2225/1076 ,  H01L2924/12042 ,  H01L2924/1815 ,  H01L2924/00

摘要： Embodiments of methods for forming a device include performing an oxidation inhibiting treatment to exposed ends of first and second device-to-edge conductors, and forming a package surface conductor to electrically couple the exposed ends of the first and second device-to-edge conductors. Performing the oxidation inhibiting treatment may include applying an organic solderability protectant coating to the exposed ends, or plating the exposed ends with a conductive plating material. The method may further include applying a conformal protective coating over the package surface conductor. An embodiment of a device formed using such a method includes a package body, the first and second device-to-edge conductors, the package surface conductor on a surface of the package body and extending between the first and second device-to-edge conductors, and the conformal protective coating over the package surface conductor.

摘要翻译： 用于形成装置的方法的实施例包括对第一和第二器件对边缘导体的暴露端执行氧化抑制处理，以及形成封装表面导体，以电耦合第一和第二器件对边缘导体的暴露端 。 执行氧化抑制处理可以包括将有机可焊性保护剂涂层施加到暴露端，或者用导电电镀材料电镀暴露端。 该方法还可以包括在包装表面导体上施加保形涂层。 使用这种方法形成的器件的实施例包括封装体，第一和第二器件对边缘导体，封装体表面上的封装表面导体，并且在第一和第二器件对边缘导体之间延伸 ，以及封装表面导体上的保形涂层。

公开(公告)号：US09257415B2

公开(公告)日：2016-02-09

申请号：US14706359

申请日：2015-05-07

申请人： Michael B. Vincent ,  Scott M. Hayes ,  Jason R. Wright ,  Zhiwei Gong

发明人： Michael B. Vincent ,  Scott M. Hayes ,  Jason R. Wright ,  Zhiwei Gong

IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L25/00 ,  H01L25/03

CPC分类号： H01L25/0657 ,  H01L21/4853 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49805 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L25/03 ,  H01L25/105 ,  H01L25/50 ,  H01L2225/06551 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/00

摘要： Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of stacked microelectronic packages. In one embodiment, the method includes producing a partially-completed stacked microelectronic package including a package body having a vertical package sidewall, a plurality microelectronic devices embedded within the package body, and package edge conductors electrically coupled to the plurality of microelectronic devices and extending to the vertical package sidewall. A flowable conductive material is applied on the vertical package sidewall and contacts the package edge conductors. Selected portions of the flowable conductive material are then removed to define, at least in part, electrically-isolated sidewall conductors electrically coupled to different ones of the package edge conductors.