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    Method of fabricating a planar structure charge trapping memory cell array with rectangular gates and reduced bit line resistance
    5.
    发明授权
    Method of fabricating a planar structure charge trapping memory cell array with rectangular gates and reduced bit line resistance 失效
    制造平面结构电荷捕获具有矩形栅极的存储单元阵列并降低位线电阻的方法

    公开(公告)号：US06855608B1

    公开(公告)日：2005-02-15

    申请号：US10463643

    申请日：2003-06-17

    申请人： Mark Ramsbey ,  Mark W. Randolph ,  Jean Yee-Mei Yang ,  Hiroyuki Kinoshita ,  Cyrus Tabery ,  Jeff P. Erhardt ,  Tazrien Kamal ,  Jaeyong Park ,  Emmanuil H. Lingunis

    发明人： Mark Ramsbey ,  Mark W. Randolph ,  Jean Yee-Mei Yang ,  Hiroyuki Kinoshita ,  Cyrus Tabery ,  Jeff P. Erhardt ,  Tazrien Kamal ,  Jaeyong Park ,  Emmanuil H. Lingunis

    IPC分类号： G11C16/04 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/105

    CPC分类号： H01L27/11568 ,  G11C16/0475 ,  G11C16/0491 ,  H01L27/105 ,  H01L27/11573

    摘要： A method of fabricating a planar architecture charge trapping dielectric memory cell array with rectangular gates comprises fabricating a multi-layer charge trapping dielectric on the surface of a substrate. The layer adjacent to the substrate may be an oxide. A polysilicon layer is deposited over the charge trapping dielectric. A word line mask is applied over the polysilicon layer to mask linear word lines in a first direction and to expose trench regions there between and the trenches are etched to expose the charge trapping dielectric in the trench regions. A bit line mask is applied over the polysilicon layer to mask gates in a second direction perpendicular to the first direction and to expose bit line regions there between and the bit lines are etched to expose the oxide in the bit line regions. The bit lines are implanted and insulating spacers are fabricated on exposed sidewalls. The oxide is removed to expose the substrate between insulating spacers in the bit line regions and a conductor is fabricated thereon to enhance conductivity of each bit line.

    摘要翻译： 制造具有矩形栅极的平面架构电荷俘获介质存储单元阵列的方法包括在衬底的表面上制造多层电荷俘获电介质。 与衬底相邻的层可以是氧化物。 在电荷捕获电介质上沉积多晶硅层。 在多晶硅层上施加字线掩模以在第一方向上屏蔽线性字线并且在其间露出沟槽区域，并且蚀刻沟槽以暴露沟槽区域中的电荷俘获电介质。 将位线掩模施加在多晶硅层上以在垂直于第一方向的第二方向上屏蔽栅极，并在其间暴露位线区域，并蚀刻位线以暴露位线区域中的氧化物。 植入位线，并在暴露的侧壁上制造绝缘间隔物。 去除氧化物以在位线区域中的绝缘间隔物之间​​露出衬底，并且在其上制造导体以增强每个位线的导电性。

    Using thin undoped TEOS with BPTEOS ILD or BPTEOS ILD alone to improve charge loss and contact resistance in multi-bit memory devices
    9.
    发明申请
    Using thin undoped TEOS with BPTEOS ILD or BPTEOS ILD alone to improve charge loss and contact resistance in multi-bit memory devices 审中-公开
    使用薄的未掺杂TEOS与BPTEOS ILD或BPTEOS ILD单独改善多位存储器件中的电荷损失和接触电阻

    公开(公告)号：US20070029604A1

    公开(公告)日：2007-02-08

    申请号：US11546688

    申请日：2006-10-12

    申请人： Ning Cheng ,  Minh Ngo ,  Hirokazu Tokuno ,  Lu You ,  Angela Hui ,  Yi He ,  Brian Mooney ,  Joan Yang ,  Mark Ramsbey

    发明人： Ning Cheng ,  Minh Ngo ,  Hirokazu Tokuno ,  Lu You ,  Angela Hui ,  Yi He ,  Brian Mooney ,  Joan Yang ,  Mark Ramsbey

    IPC分类号： H01L29/788

    CPC分类号： H01L27/115 ,  H01L27/11568

    摘要： The present invention facilitates dual bit memory devices and operation of dual bit memory device by providing systems and methods that employ a relatively thin undoped TEOS liner during fabrication, instead of a relatively thick TEOS layer that is conventionally used. Employment of the relatively thin liner facilitates dual bit memory device operation by mitigating charge loss and contact resistance while providing protection against unwanted dopant diffusion. The present invention includes utilizing a relatively thin undoped TEOS liner that is formed on wordlines and portions of a charge trapping dielectric layer. The relatively thin undoped TEOS liner is formed with a thickness of less than about 400 Angstroms so that contact resistance and charge loss are improved and yet providing suitable protection for operation of the device. Additionally, the present invention includes foregoing with an undoped TEOS liner altogether.

    摘要翻译： 本发明通过提供在制造期间使用相对薄的未掺杂TEOS衬垫的系统和方法而不是通常使用的相对较厚的TEOS层来便于双位存储器件和双位存储器件的操作。 使用相对薄的衬垫通过减轻电荷损失和接触电阻而提供双位存储器件操作，同时提供防止不期望的掺杂剂扩散的保护。 本发明包括利用形成在字线和电荷捕获电介质层的部分上的相对薄的未掺杂的TEOS衬垫。 相对薄的未掺杂的TEOS衬垫形成有小于约400埃的厚度，使得接触电阻和电荷损失得到改善，并且为器件的操作提供适当的保护。 此外，本发明包括前述的未掺杂的TEOS衬垫。

    Bit line implant
    10.
    发明申请
    Bit line implant 有权
    位线植入

    公开(公告)号：US20070093042A1

    公开(公告)日：2007-04-26

    申请号：US11254769

    申请日：2005-10-21

    申请人： Angela Hui ,  Jean Yang ,  Yu Sun ,  Mark Ramsbey ,  Weidong Qian

    发明人： Angela Hui ,  Jean Yang ,  Yu Sun ,  Mark Ramsbey ,  Weidong Qian

    IPC分类号： H01L21/04

    CPC分类号： H01L27/11568 ,  H01L27/115

    摘要： A method for performing a bit line implant is disclosed. The method includes forming a group of structures on an oxide-nitride-oxide stack of a semiconductor device. Each structure of the group of structures includes a polysilicon portion and a hard mask portion. A first structure of the group of structures is separated from a second structure of the group of structures by less than 100 nanometers. The method further includes using the first structure and the second structure to isolate a portion of the semiconductor device for the bit line implant.

    摘要翻译： 公开了一种用于执行位线植入的方法。 该方法包括在半导体器件的氧化物 - 氮化物 - 氧化物堆叠上形成一组结构。 该组结构的每个结构包括多晶硅部分和硬掩模部分。 该组结构的第一结构与该组结构的第二结构分开小于100纳米。 该方法还包括使用第一结构和第二结构来隔离位线植入物的半导体器件的一部分。