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公开(公告)号：US08749059B2
公开(公告)日：2014-06-10
申请号：US13418261
申请日：2012-03-12
CPC分类号： H01L21/02697 , H01L23/53238 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/0345 , H01L2224/03452 , H01L2224/0401 , H01L2224/05006 , H01L2224/05007 , H01L2224/05016 , H01L2224/05026 , H01L2224/05027 , H01L2224/05124 , H01L2224/05147 , H01L2224/05157 , H01L2224/05187 , H01L2224/05562 , H01L2224/05572 , H01L2224/131 , H01L2924/00014 , H01L2924/0002 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/15787 , H01L2924/04953 , H01L2924/01014 , H01L2224/05552 , H01L2924/00
摘要： Disclosed is a process of making a semiconductor device wherein an insulation layer has a copper plug in contact with the last wiring layer of the device. There may also be a barrier layer separating the copper plug from the insulation layer. There may also be a cap layer over the copper plug to protect it from oxidation. There may also be a dielectric layer over the cap layer.
摘要翻译： 公开了制造半导体器件的方法，其中绝缘层具有与器件的最后布线层接触的铜插塞。 还可以存在将铜塞与绝缘层分离的阻挡层。 在铜塞上方也可能有一个盖层，以防止它被氧化。 在盖层上还可以存在介电层。
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公开(公告)号：US08610283B2
公开(公告)日：2013-12-17
申请号：US12573183
申请日：2009-10-05
CPC分类号： H01L21/02697 , H01L23/53238 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/0345 , H01L2224/03452 , H01L2224/0401 , H01L2224/05006 , H01L2224/05007 , H01L2224/05016 , H01L2224/05026 , H01L2224/05027 , H01L2224/05124 , H01L2224/05147 , H01L2224/05157 , H01L2224/05187 , H01L2224/05562 , H01L2224/05572 , H01L2224/131 , H01L2924/00014 , H01L2924/0002 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/15787 , H01L2924/04953 , H01L2924/01014 , H01L2224/05552 , H01L2924/00
摘要： Disclosed is a semiconductor device wherein an insulation layer has a copper plug in contact with the last wiring layer of the device. There may also be a barrier layer separating the copper plug from the insulation layer. In a further embodiment, there may also be an aluminum layer between the insulation layer and copper plug. Also disclosed is a process for making the semiconductor device.
摘要翻译： 公开了一种半导体器件，其中绝缘层具有与器件的最后布线层接触的铜插塞。 还可以存在将铜塞与绝缘层分离的阻挡层。 在另一实施例中，在绝缘层和铜插塞之间也可以有铝层。 还公开了制造半导体器件的方法。
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公开(公告)号：US20120168952A1
公开(公告)日：2012-07-05
申请号：US13418261
申请日：2012-03-12
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L21/02697 , H01L23/53238 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/0345 , H01L2224/03452 , H01L2224/0401 , H01L2224/05006 , H01L2224/05007 , H01L2224/05016 , H01L2224/05026 , H01L2224/05027 , H01L2224/05124 , H01L2224/05147 , H01L2224/05157 , H01L2224/05187 , H01L2224/05562 , H01L2224/05572 , H01L2224/131 , H01L2924/00014 , H01L2924/0002 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/15787 , H01L2924/04953 , H01L2924/01014 , H01L2224/05552 , H01L2924/00
摘要： Disclosed is a process of making a semiconductor device wherein an insulation layer has a copper plug in contact with the last wiring layer of the device. There may also be a barrier layer separating the copper plug from the insulation layer. There may also be a cap layer over the copper plug to protect it from oxidation. There may also be a dielectric layer over the cap layer.
摘要翻译： 公开了制造半导体器件的方法，其中绝缘层具有与器件的最后布线层接触的铜插塞。 还可以存在将铜塞与绝缘层分离的阻挡层。 在铜塞上方也可能有一个盖层，以防止它被氧化。 在盖层上还可以存在介电层。
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公开(公告)号：US08022543B2
公开(公告)日：2011-09-20
申请号：US12054713
申请日：2008-03-25
IPC分类号： H01L23/48
CPC分类号： H01L24/11 , H01L2224/0401 , H01L2224/05018 , H01L2224/05022 , H01L2224/05026 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05181 , H01L2224/05184 , H01L2224/05558 , H01L2224/05572 , H01L2224/0558 , H01L2224/05647 , H01L2224/05655 , H01L2224/13022 , H01L2224/13099 , H01L2224/16 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2224/05552 , H01L2924/00014 , H01L2924/013
摘要： A first metallic diffusion barrier layer is formed on a last level metal plate exposed in an opening of a passivation layer. Optionally, a metallic adhesion promotion layer is formed on the first metallic diffusion barrier layer. An elemental metal conductive layer is formed on the metallic adhesion promotion layer, which provides a highly conductive structure that distributes current uniformly due to the higher electrical conductivity of the material than the layers above or below. A stack of the second metallic diffusion barrier layer and a wetting promotion layer is formed, on which a C4 ball is bonded. The elemental metal conductive layer distributes the current uniformly within the underbump metallurgy structure, which induces a more uniform current distribution in the C4 ball and enhanced electromigration resistance of the C4 ball.
摘要翻译： 第一金属扩散阻挡层形成在暴露在钝化层的开口中的最后一级金属板上。 任选地，在第一金属扩散阻挡层上形成金属粘附促进层。 在金属粘合促进层上形成元素金属导电层，其提供高导电性结构，其由于材料的导电性高于或高于上述层而导致电流均匀分布。 形成第二金属扩散阻挡层和润湿促进层的叠层，其上结合有C4球。 元素金属导电层将电流均匀分布在下焊管冶金结构内，从而在C4球中引起更均匀的电流分布，提高C4球的电迁移阻力。
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公开(公告)号：US20090243098A1
公开(公告)日：2009-10-01
申请号：US12054713
申请日：2008-03-25
CPC分类号： H01L24/11 , H01L2224/0401 , H01L2224/05018 , H01L2224/05022 , H01L2224/05026 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05181 , H01L2224/05184 , H01L2224/05558 , H01L2224/05572 , H01L2224/0558 , H01L2224/05647 , H01L2224/05655 , H01L2224/13022 , H01L2224/13099 , H01L2224/16 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2224/05552 , H01L2924/00014 , H01L2924/013
摘要： A first metallic diffusion barrier layer is formed on a last level metal plate exposed in an opening of a passivation layer. Optionally, a metallic adhesion promotion layer is formed on the first metallic diffusion barrier layer. An elemental metal conductive layer is formed on the metallic adhesion promotion layer, which provides a highly conductive structure that distributes current uniformly due to the higher electrical conductivity of the material than the layers above or below. A stack of the second metallic diffusion barrier layer and a wetting promotion layer is formed, on which a C4 ball is bonded. The elemental metal conductive layer distributes the current uniformly within the underbump metallurgy structure, which induces a more uniform current distribution in the C4 ball and enhanced electromigration resistance of the C4 ball.
摘要翻译： 第一金属扩散阻挡层形成在暴露在钝化层的开口中的最后一级金属板上。 任选地，在第一金属扩散阻挡层上形成金属粘附促进层。 在金属粘合促进层上形成元素金属导电层，其提供高导电性结构，其由于材料的导电性高于或高于上述层而导致电流均匀分布。 形成第二金属扩散阻挡层和润湿促进层的叠层，其上结合有C4球。 元素金属导电层将电流均匀分布在下焊管冶金结构内，从而在C4球中引起更均匀的电流分布，提高C4球的电迁移阻力。
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公开(公告)号：US08546961B2
公开(公告)日：2013-10-01
申请号：US12987202
申请日：2011-01-10
申请人： Mukta G. Farooq , Troy L. Graves-Abe , Robert Hannon , Emily R. Kinser , William F. Landers , Kevin S. Petrarca , Richard P. Volant , Kevin R. Winstel
发明人： Mukta G. Farooq , Troy L. Graves-Abe , Robert Hannon , Emily R. Kinser , William F. Landers , Kevin S. Petrarca , Richard P. Volant , Kevin R. Winstel
IPC分类号： H01L23/544 , H01L21/02
CPC分类号： H01L21/76898 , H01L21/8221 , H01L23/544 , H01L24/83 , H01L24/92 , H01L24/94 , H01L25/0657 , H01L2223/54426 , H01L2224/29187 , H01L2224/2919 , H01L2224/32145 , H01L2224/8385 , H01L2224/83896 , H01L2224/9202 , H01L2224/94 , H01L2225/06541 , H01L2225/06593 , H01L2924/14 , H01L2924/1431 , H01L2924/1434 , H01L2924/1436 , H01L2224/83
摘要： Disclosed are a structure including alignment marks and a method of forming alignment marks in three dimensional (3D) structures. The method includes forming apertures in a first surface of a first semiconductor substrate; joining the first surface of the first semiconductor substrate to a first surface of a second semiconductor substrate; thinning the first semiconductor on a second surface of the first semiconductor substrate to provide optical contrast between the apertures and the first semiconductor substrate; and aligning a feature on the second surface of the first semiconductor substrate using the apertures as at least one alignment mark.
摘要翻译： 公开了包括对准标记的结构和在三维（3D）结构中形成对准标记的方法）。 该方法包括在第一半导体衬底的第一表面中形成孔; 将第一半导体衬底的第一表面接合到第二半导体衬底的第一表面; 在第一半导体衬底的第二表面上使第一半导体薄化以提供孔和第一半导体衬底之间的光学对比度; 以及使用所述孔将所述第一半导体衬底的所述第二表面上的特征对准为至少一个对准标记。
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公开(公告)号：US08039964B2
公开(公告)日：2011-10-18
申请号：US12038241
申请日：2008-02-27
申请人： Mukta G. Farooq , Emily R. Kinser
发明人： Mukta G. Farooq , Emily R. Kinser
CPC分类号： H01L21/76831 , H01L21/76807 , H01L21/76814 , H01L21/76826 , H01L21/76829 , H01L23/5226 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2224/05001 , H01L2224/05022 , H01L2224/05027 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05572 , H01L2224/05639 , H01L2224/05644 , H01L2224/05666 , H01L2224/11 , H01L2224/13006 , H01L2924/0002 , H01L2924/00 , H01L2924/00014
摘要： A line trough and a via cavity are formed within a dielectric layer comprising a fluorosilicate glass (FSG) layer. A fluorine depleted adhesion layer is formed within the line trough and the via cavity either by a plasma treatment that removes fluorine from exposed surfaces of the FSG layer, or by deposition of a substantially fluorine-free dielectric layer. Metal is deposited within the line trough and the via cavity to form a metal line and a metal via. The fluorine depleted adhesion layer provides enhanced adhesion to the metal line compared with prior art structures in which a metal line directly contacts a FSG layer. The enhanced adhesion of metal with an underlying dielectric layer provides higher resistance to delamination for a semiconductor package employing lead-free C4 balls on a metal interconnect structure.
摘要翻译： 在包含氟硅酸盐玻璃（FSG）层的电介质层内形成线槽和通孔。 通过从FSG层的暴露表面除去氟的等离子体处理或通过沉积基本上无氟的介电层，在管线槽和通孔内形成氟贫化粘合层。 金属沉积在管线槽和通孔腔内以形成金属线和金属通孔。 与其中金属线直接接触FSG层的现有技术结构相比，氟贫化粘合层提供对金属线的增强的粘合性。 金属与底层电介质层的增强的粘附性对于在金属互连结构上使用无铅C4球的半导体封装提供更高的剥离性。
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公开(公告)号：US20110171827A1
公开(公告)日：2011-07-14
申请号：US12687282
申请日：2010-01-14
申请人： Mukta G. Farooq , Emily R. Kinser , Richard Wise , Hakeem Yusuff
发明人： Mukta G. Farooq , Emily R. Kinser , Richard Wise , Hakeem Yusuff
IPC分类号： H01L21/768
CPC分类号： H01L21/76847 , H01L21/0337 , H01L21/32136 , H01L21/76898 , H01L23/481 , H01L25/0657 , H01L25/50 , H01L2225/06541 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A method includes patterning a photoresist layer on a structure to define an opening and expose a first planar area on a substrate layer, etching the exposed planar area to form a cavity having a first depth in the structure, removing a second portion of the photoresist to expose a second planar area on the substrate layer, forming a doped portion in the second planar area, and etching the cavity to expose a first conductor in the structure and the doped portion to expose a second conductor in the structure.
摘要翻译： 一种方法包括在结构上图案化光致抗蚀剂层以限定开口并暴露衬底层上的第一平面区域，蚀刻暴露的平面区域以形成在结构中具有第一深度的空腔，将光致抗蚀剂的第二部分去除 在衬底层上露出第二平面区域，在第二平面区域中形成掺杂部分，并且蚀刻腔体以暴露结构中的第一导体和掺杂部分以暴露结构中的第二导体。
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9.发明授权公开(公告)号：US08492252B2
公开(公告)日：2013-07-23
申请号：US13422445
申请日：2012-03-16
申请人： Mukta G. Farooq , Emily R. Kinser , Richard Wise , Hakeem Yusuff
发明人： Mukta G. Farooq , Emily R. Kinser , Richard Wise , Hakeem Yusuff
IPC分类号： H01L21/265
CPC分类号： H01L21/76847 , H01L21/0337 , H01L21/32136 , H01L21/76898 , H01L23/481 , H01L25/0657 , H01L25/50 , H01L2225/06541 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A method includes patterning a photoresist layer on a structure to define an opening and expose a first planar area on a substrate layer, forming doped portions of the substrate layer in the first planar area, removing a portion of the photoresist to form a second opening defining a second planar area on the substrate layer, and etching to form a first cavity having a first depth defined by the first opening to expose a first contact in the structure and to form a second cavity defined by the second opening to expose a second contact in the structure.
摘要翻译： 一种方法包括在结构上图案化光致抗蚀剂层以限定开口并暴露衬底层上的第一平面区域，在第一平面区域中形成衬底层的掺杂部分，去除光致抗蚀剂的一部分以形成限定 在衬底层上的第二平面区域，以及蚀刻形成具有由第一开口限定的第一深度的第一腔体，以暴露结构中的第一接触件，并形成由第二开口限定的第二腔室，以暴露第二接触件 结构。
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公开(公告)号：US20130069062A1
公开(公告)日：2013-03-21
申请号：US13233085
申请日：2011-09-15
CPC分类号： H01L22/34 , H01L23/481 , H01L23/58 , H01L25/0657 , H01L2924/0002 , H01L2924/00
摘要： A leakage measurement structure for through substrate vias which includes a semiconductor substrate; a plurality of through substrate vias in the semiconductor substrate extending substantially through the semiconductor substrate; and a leakage measurement structure located in the semiconductor substrate. The leakage measurement structure includes a plurality of substrate contacts extending into the semiconductor substrate; a plurality of sensing circuits connected to the plurality of through substrate vias and to the plurality of the substrate contacts, the plurality of sensing circuits providing a plurality of outputs indicative of current leakage from the plurality of through substrate vias; a built-in self test (BIST) engine to step through testing of the plurality of through substrate vias; and a memory coupled to the BIST engine to receive the outputs from the plurality of sensing circuits. Also included is a method of testing a semiconductor substrate having a plurality of through substrate vias for current leakage.
摘要翻译： 一种用于通过衬底通孔的泄漏测量结构，其包括半导体衬底; 半导体衬底中的多个穿过衬底通孔，其基本上延伸穿过半导体衬底; 以及位于半导体衬底中的泄漏测量结构。 泄漏测量结构包括延伸到半导体衬底中的多个衬底触点; 多个感测电路，连接到多个通过衬底通孔和多个衬底触点，所述多个感测电路提供指示来自多个通过衬底通孔的电流泄漏的多个输出; 一个内置的自检（BIST）引擎，逐步测试多个通过基板通孔; 以及耦合到BIST引擎以接收来自多个感测电路的输出的存储器。 还包括一种测试半导体衬底的方法，该半导体衬底具有用于电流泄漏的多个通过衬底通孔。
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