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28 条记录 (耗时 0.035 秒)

    OPTIMIZED ANNULAR COPPER TSV
    3.
    发明申请
    OPTIMIZED ANNULAR COPPER TSV 有权
    优化的环形铜片TSV

    公开(公告)号：US20120326309A1

    公开(公告)日：2012-12-27

    申请号：US13167107

    申请日：2011-06-23

    申请人： PAUL S ANDRY ,  Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer ,  Emily R. Kinser ,  Cornelia K. Tsang ,  Richard P. Volant

    发明人： PAUL S ANDRY ,  Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer ,  Emily R. Kinser ,  Cornelia K. Tsang ,  Richard P. Volant

    IPC分类号： H01L23/48 ,  H01L21/283

    CPC分类号： H01L21/76846 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present disclosure provides a thermo-mechanically reliable copper TSV and a technique to form such TSV during BEOL processing. The TSV constitutes an annular trench which extends through the semiconductor substrate. The substrate defines the inner and outer sidewalls of the trench, which sidewalls are separated by a distance within the range of 5 to 10 microns. A conductive path comprising copper or a copper alloy extends within said trench from an upper surface of said first dielectric layer through said substrate. The substrate thickness can be 60 microns or less. A dielectric layer having interconnect metallization conductively connected to the conductive path is formed directly over said annular trench.

    摘要翻译： 本公开提供了热机械可靠的铜TSV和在BEOL处理期间形成这种TSV的技术。 TSV构成延伸穿过半导体衬底的环形沟槽。 衬底限定沟槽的内侧壁和外侧壁，该侧壁分隔5至10微米的距离。 包括铜或铜合金的导电路径从所述第一介电层的上表面通过所述衬底在所述沟槽内延伸。 基板厚度可以为60微米或更小。 具有导电连接到导电路径的互连金属化的电介质层直接形成在所述环形沟槽上。

    LEAKAGE MEASUREMENT OF THROUGH SILICON VIAS
    8.
    发明申请
    LEAKAGE MEASUREMENT OF THROUGH SILICON VIAS 有权
    通过硅胶渗漏测量

    公开(公告)号：US20130069062A1

    公开(公告)日：2013-03-21

    申请号：US13233085

    申请日：2011-09-15

    申请人： Bhavana Bhoovaraghan ,  Mukta G. Farooq ,  Emily R. Kinser ,  Sudesh Saroop

    发明人： Bhavana Bhoovaraghan ,  Mukta G. Farooq ,  Emily R. Kinser ,  Sudesh Saroop

    IPC分类号： H01L23/58 ,  H01L21/66

    CPC分类号： H01L22/34 ,  H01L23/481 ,  H01L23/58 ,  H01L25/0657 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A leakage measurement structure for through substrate vias which includes a semiconductor substrate; a plurality of through substrate vias in the semiconductor substrate extending substantially through the semiconductor substrate; and a leakage measurement structure located in the semiconductor substrate. The leakage measurement structure includes a plurality of substrate contacts extending into the semiconductor substrate; a plurality of sensing circuits connected to the plurality of through substrate vias and to the plurality of the substrate contacts, the plurality of sensing circuits providing a plurality of outputs indicative of current leakage from the plurality of through substrate vias; a built-in self test (BIST) engine to step through testing of the plurality of through substrate vias; and a memory coupled to the BIST engine to receive the outputs from the plurality of sensing circuits. Also included is a method of testing a semiconductor substrate having a plurality of through substrate vias for current leakage.

    摘要翻译： 一种用于通过衬底通孔的泄漏测量结构，其包括半导体衬底; 半导体衬底中的多个穿过衬底通孔，其基本上延伸穿过半导体衬底; 以及位于半导体衬底中的泄漏测量结构。 泄漏测量结构包括延伸到半导体衬底中的多个衬底触点; 多个感测电路，连接到多个通过衬底通孔和多个衬底触点，所述多个感测电路提供指示来自多个通过衬底通孔的电流泄漏的多个输出; 一个内置的自检（BIST）引擎，逐步测试多个通过基板通孔; 以及耦合到BIST引擎以接收来自多个感测电路的输出的存储器。 还包括一种测试半导体衬底的方法，该半导体衬底具有用于电流泄漏的多个通过衬底通孔。