公开(公告)号：US20080038913A1

公开(公告)日：2008-02-14

申请号：US11463642

申请日：2006-08-10

申请人： Mukta G. Farooq ,  Robert Hannon ,  Ian D. Melville ,  Kevin S. Petrarca ,  Donna S. Zupanski-Nielsen

发明人： Mukta G. Farooq ,  Robert Hannon ,  Ian D. Melville ,  Kevin S. Petrarca ,  Donna S. Zupanski-Nielsen

IPC分类号： H01L21/44

CPC分类号： H01L24/02 ,  H01L24/45 ,  H01L2224/04042 ,  H01L2224/45144 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2224/48

摘要： Methods of forming an aluminum-free wire bond pad and the pad so formed are disclosed. In one embodiment, the method includes forming an opening through a dielectric layer to a last metal of a chip; forming a tantalum nitride (TaN) layer over the chip and over the opening; removing the tantalum nitride (TaN) layer outside of the opening; forming a passivation mask layer over the chip including a passivation mask opening over the last metal; forming a titanium tungsten (TiW) layer and a copper (Cu) layer over the chip; forming a mask layer over the chip including a mask opening to the copper (Cu) layer over the last metal; forming a nickel (Ni) layer and a copper (Cu) layer and then a gold (Au) layer in the mask opening; and removing the mask.

摘要翻译： 公开了形成无铝线接合焊盘和如此形成的焊盘的方法。 在一个实施例中，该方法包括通过电介质层形成开口至芯片的最后一个金属; 在芯片上并在开口上形成氮化钽（TaN）层; 去除开口外面的氮化钽（TaN）层; 在所述芯片上形成钝化掩模层，其包括在最后一个金属上的钝化掩模开口; 在芯片上形成钛钨（TiW）层和铜（Cu）层; 在所述芯片上形成掩模层，所述掩模层包括在最后金属上的铜（Cu）层的掩模开口; 在掩模开口中形成镍（Ni）层和铜（Cu）层，然后形成金（Au）层; 并取下面罩。

公开(公告)号：US20080029898A1

公开(公告)日：2008-02-07

申请号：US11461511

申请日：2006-08-01

申请人： Mukta G. Farooq ,  Robert Hannon ,  Dae Young Jung ,  Ian D. Melville ,  Donna S. Zupanski-Nielsen

发明人： Mukta G. Farooq ,  Robert Hannon ,  Dae Young Jung ,  Ian D. Melville ,  Donna S. Zupanski-Nielsen

IPC分类号： H01L23/48

CPC分类号： H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： Via stack structures are disclosed. In one embodiment, a structure includes a via stack including: a first substantially cross-shaped line in a first dielectric layer; a second substantially cross-shaped line set in a second dielectric layer, and a via stud coupling the first substantially cross-shaped line to the second substantially cross-shaped line. In another embodiment, a structure includes a first via stack, and a second via stack, wherein the first via stack and the second via stack extend in a divergent manner from one another. Each via stack structure is useful for support, for example, in under wire bond applications. The via stack structures can be mixed with other via stack structures and selectively placed within a layout to replace conventional metal plate and via stud array configurations.

摘要翻译： 公开了通过堆叠结构。 在一个实施例中，结构包括通孔堆叠，其包括：第一介电层中的第一基本十字形的线; 设置在第二电介质层中的第二基本上十字形的线，以及将第一基本上十字形的线耦合到第二基本十字形线的通孔柱。 在另一个实施例中，结构包括第一通孔堆叠和第二通孔堆叠，其中第一通孔堆叠和第二通孔堆叠以彼此发散的方式延伸。 每个通孔堆叠结构可用于支持，例如在引线键合应用中。 通孔堆叠结构可以与其它通孔堆叠结构混合并且选择性地放置在布局内以代替传统的金属板和经由螺柱阵列配置。

公开(公告)号：US08120175B2

公开(公告)日：2012-02-21

申请号：US11947832

申请日：2007-11-30

申请人： Mukta G. Farooq ,  Ian D. Melville ,  Kevin S. Petrarca

发明人： Mukta G. Farooq ,  Ian D. Melville ,  Kevin S. Petrarca

IPC分类号： H01L23/48

CPC分类号： H01L24/16 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05568 ,  H01L2224/10126 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/05541 ,  H01L2224/05005

摘要： A method creates a structure that comprises a carrier connected to an integrated circuit chip by pillars and openings. Thus, in this structure, at least one conductive pillar extends a distance or height from the surface of the integrated circuit chip and a barrier surrounds the lower portion of the conductive pillar such that the barrier covers at least some portion of the height of the pillar that is closest to the chip surface. There is at least one opening in the carrier that is large enough to accommodate the conductive pillar and the barrier, and the conductive pillar and the barrier are positioned in opening. A solder is used in the bottom of the opening to connect the conductive pillar to the bottom of the opening. The barrier prevents the solder from contacting the portion of the conductive pillar protected by the barrier.

摘要翻译： 一种方法产生一种结构，其包括通过柱和开口连接到集成电路芯片的载体。 因此，在这种结构中，至少一个导电柱与集成电路芯片的表面延伸一段距离或高度，并且阻挡层围绕导电柱的下部，使得阻挡层覆盖柱的高度的至少一部分 最接近芯片表面。 载体中至少有一个开口足够大以容纳导电柱和屏障，并且导电柱和屏障位于开口中。 在开口的底部使用焊料将导电柱连接到开口的底部。 屏障防止焊料接触由屏障保护的导电柱的部分。

公开(公告)号：US20090140420A1

公开(公告)日：2009-06-04

申请号：US11947832

申请日：2007-11-30

申请人： Mukta G. Farooq ,  Ian D. Melville ,  Kevin S. Petrarca

发明人： Mukta G. Farooq ,  Ian D. Melville ,  Kevin S. Petrarca

IPC分类号： H01L23/488 ,  H01L21/44

CPC分类号： H01L24/16 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05568 ,  H01L2224/10126 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/05541 ,  H01L2224/05005

摘要： A method creates a structure that comprises a carrier connected to an integrated circuit chip by pillars and openings. Thus, in this structure, at least one conductive pillar extends a distance or height from the surface of the integrated circuit chip and a barrier surrounds the lower portion of the conductive pillar such that the barrier covers at least some portion of the height of the pillar that is closest to the chip surface. There is at least one opening in the carrier that is large enough to accommodate the conductive pillar and the barrier, and the conductive pillar and the barrier are positioned in opening. A solder is used in the bottom of the opening to connect the conductive pillar to the bottom of the opening. The barrier prevents the solder from contacting the portion of the conductive pillar protected by the barrier.

摘要翻译： 一种方法产生一种结构，其包括通过柱和开口连接到集成电路芯片的载体。 因此，在这种结构中，至少一个导电柱与集成电路芯片的表面延伸一段距离或高度，并且阻挡层围绕导电柱的下部，使得阻挡层覆盖柱的高度的至少一部分 最接近芯片表面。 载体中至少有一个开口足够大以容纳导电柱和屏障，并且导电柱和屏障位于开口中。 在开口的底部使用焊料将导电柱连接到开口的底部。 屏障防止焊料接触由屏障保护的导电柱的部分。

公开(公告)号：US20090039515A1

公开(公告)日：2009-02-12

申请号：US11836819

申请日：2007-08-10

申请人： Mukta G. Farooq ,  Ian D. Melville ,  Kevin S. Petrarca ,  Kenneth P. Rodbell

发明人： Mukta G. Farooq ,  Ian D. Melville ,  Kevin S. Petrarca ,  Kenneth P. Rodbell

IPC分类号： H01L21/44 ,  H01L23/48

CPC分类号： H01L23/5329 ,  H01L23/556 ,  H01L2924/0002 ,  Y10S438/958 ,  Y10S438/967 ,  H01L2924/00

摘要： Methods of blocking ionizing radiation to reduce soft errors and resulting IC chips are disclosed. One embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming at least one back end of line (BEOL) dielectric layer including ionizing radiation blocking material therein. Another embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming an ionizing radiation blocking layer positioned in a back end of line (BEOL) of the IC chip. The ionizing radiation blocking material or layer absorbs ionizing radiation and reduces soft errors within the IC chip.

摘要翻译： 公开了阻止电离辐射以减少软错误的方法和产生的IC芯片。 一个实施例包括形成用于集成电路（IC）芯片的线路前端（FEOL）; 以及在其中形成包括其中的电离辐射阻挡材料的至少一个后端线（BEOL）电介质层。 另一实施例包括形成用于集成电路（IC）芯片的线路前端（FEOL）; 以及形成位于IC芯片的后端（BEOL）的电离辐射阻挡层。 电离辐射阻挡材料或层吸收电离辐射并减少IC芯片内的软误差。

公开(公告)号：US10784200B2

公开(公告)日：2020-09-22

申请号：US13409643

申请日：2012-03-01

申请人： Mukta G. Farooq ,  Ian D. Melville ,  Kevin S. Petrarca ,  Kenneth P. Rodbell

发明人： Mukta G. Farooq ,  Ian D. Melville ,  Kevin S. Petrarca ,  Kenneth P. Rodbell

IPC分类号： H01L23/532 ,  H01L23/556

摘要： Methods of blocking ionizing radiation to reduce soft errors and resulting IC chips are disclosed. One embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming at least one back end of line (BEOL) dielectric layer including ionizing radiation blocking material therein. Another embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming an ionizing radiation blocking layer positioned in a back end of line (BEOL) of the IC chip. The ionizing radiation blocking material or layer absorbs ionizing radiation and reduces soft errors within the IC chip.

公开(公告)号：US08445374B2

公开(公告)日：2013-05-21

申请号：US13361057

申请日：2012-01-30

申请人： Mukta G. Farooq ,  Ian D. Melville ,  Kevin S. Petrarca

发明人： Mukta G. Farooq ,  Ian D. Melville ,  Kevin S. Petrarca

IPC分类号： H01L21/44

CPC分类号： H01L24/16 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05568 ,  H01L2224/10126 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/05541 ,  H01L2224/05005

摘要： A method creates a structure that comprises a carrier connected to an integrated circuit chip by pillars and openings. Thus, in this structure, at least one conductive pillar extends a distance or height from the surface of the integrated circuit chip and a barrier surrounds the lower portion of the conductive pillar such that the barrier covers at least some portion of the height of the pillar that is closest to the chip surface. There is at least one opening in the carrier that is large enough to accommodate the conductive pillar and the barrier, and the conductive pillar and the barrier are positioned in opening. A solder is used in the bottom of the opening to connect the conductive pillar to the bottom of the opening. The barrier prevents the solder from contacting the portion of the conductive pillar protected by the barrier.

摘要翻译： 一种方法产生一种结构，其包括通过柱和开口连接到集成电路芯片的载体。 因此，在这种结构中，至少一个导电柱与集成电路芯片的表面延伸一段距离或高度，并且阻挡层围绕导电柱的下部，使得阻挡层覆盖柱的高度的至少一部分 最接近芯片表面。 载体中至少有一个开口足够大以容纳导电柱和屏障，并且导电柱和屏障位于开口中。 在开口的底部使用焊料将导电柱连接到开口的底部。 屏障防止焊料接触由屏障保护的导电柱的部分。

公开(公告)号：US08999764B2

公开(公告)日：2015-04-07

申请号：US11836819

申请日：2007-08-10

申请人： Mukta G. Farooq ,  Ian D. Melville ,  Kevin S. Petrarca ,  Kenneth P. Rodbell

发明人： Mukta G. Farooq ,  Ian D. Melville ,  Kevin S. Petrarca ,  Kenneth P. Rodbell

IPC分类号： H01L21/00 ,  H01L23/532 ,  H01L23/556

CPC分类号： H01L23/5329 ,  H01L23/556 ,  H01L2924/0002 ,  Y10S438/958 ,  Y10S438/967 ,  H01L2924/00

摘要： Methods of blocking ionizing radiation to reduce soft errors and resulting IC chips are disclosed. One embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming at least one back end of line (BEOL) dielectric layer including ionizing radiation blocking material therein. Another embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming an ionizing radiation blocking layer positioned in a back end of line (BEOL) of the IC chip. The ionizing radiation blocking material or layer absorbs ionizing radiation and reduces soft errors within the IC chip.

摘要翻译： 公开了阻止电离辐射以减少软错误的方法和产生的IC芯片。 一个实施例包括形成用于集成电路（IC）芯片的线路前端（FEOL）; 以及在其中形成包括其中的电离辐射阻挡材料的至少一个后端线（BEOL）电介质层。 另一实施例包括形成用于集成电路（IC）芯片的线路前端（FEOL）; 以及形成位于IC芯片的后端（BEOL）的电离辐射阻挡层。 电离辐射阻挡材料或层吸收电离辐射并减少IC芯片内的软误差。

公开(公告)号：US07816248B2

公开(公告)日：2010-10-19

申请号：US12138482

申请日：2008-06-13

申请人： Mukta G. Farooq ,  Lacrtis Economikos ,  Ian D. Melville ,  Kevin S. Petrarca ,  Richard P. Volant

发明人： Mukta G. Farooq ,  Lacrtis Economikos ,  Ian D. Melville ,  Kevin S. Petrarca ,  Richard P. Volant

IPC分类号： H01L21/44

CPC分类号： H01L24/10 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/05085 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

摘要： Disclosed are embodiments of a far back end of the line solder connector and a method of forming the connector that eliminates the use aluminum, protects the integrity of the ball limiting metallurgy (BLM) layers and promotes adhesion of the BLM layers by incorporating a thin conformal conductive liner into the solder connector structure. This conductive liner coats the top of the via filling in any divots in order to create a uniform surface for BLM deposition and to, thereby, protect the integrity of the BLM layers. The liner further coats the dielectric sidewalls of the well in which the BLM layers are formed in order to enhance adhesion of the BLM layers to the well.

摘要翻译： 公开了线焊料连接器的远端的实施例以及形成连接器的方法，其消除了使用铝，保护了球限制冶金（BLM）层的完整性，并且通过并入薄的保形膜来促进BLM层的粘附 导电衬里进入焊接接头结构。 该导电衬里以通孔填充物的顶部涂覆任何刻痕，以便产生用于BLM沉积的均匀表面，从而保护BLM层的完整性。 衬垫还涂覆在其中形成BLM层的阱的电介质侧壁，以便增强BLM层与阱的粘合性。

公开(公告)号：US20080248643A1

公开(公告)日：2008-10-09

申请号：US12138482

申请日：2008-06-13

申请人： Mukta G. Farooq ,  Laertis Economikos ,  Ian D. Melville ,  Kevin S. Petrarca ,  Richard P. Volant

发明人： Mukta G. Farooq ,  Laertis Economikos ,  Ian D. Melville ,  Kevin S. Petrarca ,  Richard P. Volant

IPC分类号： H01L21/44

CPC分类号： H01L24/10 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/05085 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

摘要： Disclosed are embodiments of a far back end of the line solder connector and a method of forming the connector that eliminates the use aluminum, protects the integrity of the ball limiting metallurgy (BLM) layers and promotes adhesion of the BLM layers by incorporating a thin conformal conductive liner into the solder connector structure. This conductive liner coats the top of the via filling in any divots in order to create a uniform surface for BLM deposition and to, thereby, protect the integrity of the BLM layers. The liner further coats the dielectric sidewalls of the well in which the BLM layers are formed in order to enhance adhesion of the BLM layers to the well.

摘要翻译： 公开了线焊料连接器的远端的实施例以及形成连接器的方法，其消除了使用铝，保护了球限制冶金（BLM）层的完整性，并且通过并入薄的保形膜来促进BLM层的粘附 导电衬里进入焊接接头结构。 该导电衬里以通孔填充物的顶部涂覆任何刻痕，以便产生用于BLM沉积的均匀表面，从而保护BLM层的完整性。 衬垫还涂覆在其中形成BLM层的阱的电介质侧壁，以便增强BLM层与阱的粘合性。