公开(公告)号：US20160266804A1

公开(公告)日：2016-09-15

申请号：US14852398

申请日：2015-09-11

申请人： Naoki SHIMIZU

发明人： Naoki SHIMIZU

IPC分类号： G06F3/06

CPC分类号： G11C11/1673 ,  G06F13/161 ,  G11C11/1693 ,  G11C13/004 ,  G11C13/0061

摘要： According to one embodiment, a memory device includes a memory area; and a control circuit, in response to a first command, configured to read out data from the memory area without outputting the data to a data line, subsequently, in response to a second command, configured to output the data to the data line, if the first command is not received after receiving an active command, in response to the second command, configured to output the data read out from the memory area to the data line.

摘要翻译： 根据一个实施例，存储器装置包括存储区域; 以及控制电路，响应于第一命令，被配置为从存储器区域读出数据而不将数据输出到数据线，随后响应于第二命令将数据输出到数据线，如果 在接收到有效命令之后，响应于第二命令，第一命令被配置为将从存储器区域读出的数据输出到数据线。

公开(公告)号：US20160064061A1

公开(公告)日：2016-03-03

申请号：US14644152

申请日：2015-03-10

申请人： Naoki SHIMIZU

发明人： Naoki SHIMIZU

IPC分类号： G11C11/16 ,  G11C29/52 ,  G11C29/08

CPC分类号： G11C11/1677 ,  G11C7/08 ,  G11C7/12 ,  G11C7/22 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1675 ,  G11C11/1693 ,  G11C29/52 ,  G11C2029/0411

摘要： According to one embodiment, a semiconductor memory includes a memory area; an error detection circuit which detect an error of first data output from the memory area; and a control circuit which control the memory area and the error detection circuit. When the error is detected in the first data, the control circuit starts precharge of a bit line at a timing when a first period has elapsed from a start of a first operation of the memory area for output of the first data. When the error is not detected in the first data, the control circuit starts the precharge at a timing when a second period has elapsed from the start of the first operation, the second period is shorter than the first period.

摘要翻译： 根据一个实施例，半导体存储器包括存储区域; 检测从存储区域输出的第一数据的错误的错误检测电路; 以及控制电路，其控制存储区域和误差检测电路。 当在第一数据中检测到错误时，控制电路在从用于输出第一数据的存储区域的第一操作开始经过第一周期的定时开始对位线进行预充电。 当在第一数据中未检测到错误时，控制电路在从第一操作开始经过第二周期的时刻开始预充电，第二周期比第一周期短。

公开(公告)号：US20100220426A1

公开(公告)日：2010-09-02

申请号：US12784553

申请日：2010-05-21

申请人： Naoki SHIMIZU

发明人： Naoki SHIMIZU

IPC分类号： H01G4/228 ,  H01C7/18

CPC分类号： H01G4/30 ,  H01G4/012 ,  H01G4/12

摘要： A multilayer ceramic capacitor includes first internal electrodes extending to a first end surface of a ceramic element assembly, a plurality of second internal electrodes extending to a second end surface, floating internal electrodes arranged so as to overlap the first and second internal electrodes with ceramic layers disposed therebetween to define first and second effective regions, inner conductors that are elongated from the first end surface beyond a region that overlaps the first effective region in the direction of layering, and a relationship X1

摘要翻译： 多层陶瓷电容器包括延伸到陶瓷元件组件的第一端面的第一内部电极，延伸到第二端面的多个第二内部电极，布置成与第一和第二内部电极重叠的陶瓷层的浮动内部电极 设置在它们之间以限定第一和第二有效区域，内部导体从第一端面延伸超过在分层方向上与第一有效区域重叠的区域，并且满足X1

公开(公告)号：US20150345970A1

公开(公告)日：2015-12-03

申请号：US14760898

申请日：2013-01-21

申请人： Kouhei TANAKA ,  Masaya AKIHARA ,  Mitsuo SHIMOTANI ,  Naoki SHIMIZU ,  Toshio KAWAGISHI

发明人： Kouhei TANAKA ,  Masaya AKIHARA ,  Mitsuo SHIMOTANI ,  Toshio KAWAGISHI ,  Naoki SHIMIZU

IPC分类号： G01C21/34 ,  G01C21/36

CPC分类号： G01C21/3484 ,  G01C21/36 ,  G01C21/3617

摘要： It is an object of the present invention to predict a destination easily, and a destination display method for displaying a predicted destination. The destination prediction apparatus of the present invention includes: a behavior history acquiring unit that acquires, the behavior history; a visit history acquiring unit that acquires the visit history; a similar behavior date-and-time extractor that performs a similarity determination between a behavior within a predetermined period prior to a present date and time and a behavior in another period with reference to the behavior history and that extracts a date and time of the behavior in another period determined to be similar as a similar behavior date and time from the behavior history; and a destination candidate extractor that extracts, as a destination candidate, a location visited within a predetermined period before or after the similar behavior date and time from the visit history.

摘要翻译： 本发明的目的是容易地预测目的地，以及用于显示预测目的地的目的地显示方法。 本发明的目的地预测装置包括：行为历史获取单元，其获取行为历史; 获取访问历史的访问历史获取单元; 类似的行为日期和时间提取器，其执行在当前日期和时间之前的预定时间段内的行为与参考行为历史的另一时段中的行为之间的相似性确定，并提取行为的日期和时间 在另一个时期被确定为与行为历史相似的行为日期和时间; 以及目的地候选提取器，其从访问历史中提取在相似行为日期和时间之前或之后的预定时段内作为目的地候选者访问的位置。

公开(公告)号：US20150336396A1

公开(公告)日：2015-11-26

申请号：US14719679

申请日：2015-05-22

申请人： Yuichi AIHARA ,  Naoki SHIMIZU

发明人： Yuichi AIHARA ,  Naoki SHIMIZU

IPC分类号： B41J2/325

CPC分类号： B41J2/325 ,  B41J11/0005 ,  B65H15/00 ,  B65H29/125 ,  B65H29/70 ,  B65H2301/132 ,  B65H2301/51212 ,  B65H2301/51256 ,  B65H2403/512 ,  B65H2404/1421 ,  B65H2511/222 ,  B65H2511/413 ,  B65H2511/416 ,  B65H2513/11 ,  B65H2513/53 ,  B65H2515/40 ,  B65H2515/83 ,  B65H2701/1914 ,  B65H2220/02 ,  B65H2220/11 ,  B65H2220/01

摘要： To provide a transfer apparatus correcting a curl of a card efficiently while preventing the card from deteriorating, a printing apparatus includes a transfer section transferring a transfer surface of a transfer film to the card, a rotating unit reversing the front side and back side of the card in two-sided transfer, a decurl mechanism correcting a curl of the card with the transfer surface transferred in the transfer section, and a control section controlling the decurl mechanism. The control section controls the decurl mechanism such that a correction amount for the card with the transfer surface transferred to one surface in two-sided transfer is smaller than a correction amount for the card in one-sided transfer, and that the total sum of correction amounts for respective surfaces of the card in two-sided transfer is smaller than the correction amount for the card in one-sided transfer.

摘要翻译： 为了提供一种在防止卡劣化的同时有效地校正卡的卷曲的传送装置，打印装置包括将转印膜的转印面传送到卡的转印部，使转印膜的正面和背面反转的旋转单元 卡片以双面传送方式，一个去卷缩机构，用于校正传送在传送部分中的传送表面的卡片的卷曲;以及控制部分，控制分解机构。 控制部分控制分解机构，使得在双面传送中传送到一个表面的传送表面的卡的校正量小于单面传送中的卡的校正量，并且校正总和 卡片在双面传送中的各个表面的量小于单面传送中的卡的校正量。

公开(公告)号：US20150262631A1

公开(公告)日：2015-09-17

申请号：US14482925

申请日：2014-09-10

申请人： Naoki SHIMIZU

发明人： Naoki SHIMIZU

IPC分类号： G11C7/10 ,  G11C5/06 ,  G11C14/00

CPC分类号： G11C7/1072 ,  G11C7/1018 ,  G11C7/1045 ,  G11C7/20 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2207/229 ,  G11C2213/79 ,  G11C2213/82

摘要： According to one embodiment, there is provided a semiconductor memory device comprising: a memory cell array including a plurality of memory cells configured to be able to store data; a control circuit configured to control a write operation of data in the memory cell array, and an initialization operation of the memory cell array; and a register control circuit configured to receive a first command including second information for selecting first information relating to control of a cycle of a clock from completion of the write operation of data in the memory cell array to initialization of the memory cell array.

摘要翻译： 根据一个实施例，提供了一种半导体存储器件，包括：存储单元阵列，包括被配置为能够存储数据的多个存储器单元; 控制电路，被配置为控制存储单元阵列中的数据的写入操作，以及存储单元阵列的初始化操作; 以及寄存器控制电路，被配置为接收包括第二信息的第一命令，所述第二信息用于从完成存储单元阵列中的数据的写入操作到存储器单元阵列的初始化，选择与时钟周期的控制有关的第一信息。

公开(公告)号：US20150063015A1

公开(公告)日：2015-03-05

申请号：US14201618

申请日：2014-03-07

申请人： Naoki SHIMIZU

发明人： Naoki SHIMIZU

IPC分类号： G11C11/16

CPC分类号： G11C11/1653 ,  G11C7/1093 ,  G11C8/10 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0061 ,  G11C13/0069

摘要： A semiconductor memory device includes: banks each including a memory cell array; word lines connected to rows of each of the banks; an address latch circuit configured to latch a full address for specifying one of the word lines, the full address including a first address and a second address; and a control circuit configured to ignore a reset operation for the first address as a target of a set operation, and overwrite the first address in accordance with the set operation when receiving a first command for specifying a reset operation for a bank and a set operation for the first address.

摘要翻译： 半导体存储器件包括：各自包括存储单元阵列的存储体; 连接到每个银行的行的字线; 地址锁存电路，被配置为锁存用于指定字线之一的完整地址，所述完整地址包括第一地址和第二地址; 以及控制电路，被配置为忽略作为设置操作的目标的第一地址的复位操作，并且当接收到用于指定用于组的复位操作的第一命令和设置操作时，根据设置操作重写第一地址 为第一个地址。

公开(公告)号：US20150035932A1

公开(公告)日：2015-02-05

申请号：US14446713

申请日：2014-07-30

申请人： Yuichi AIHARA ,  Naoki SHIMIZU ,  Tomohisa KOIKE

发明人： Yuichi AIHARA ,  Naoki SHIMIZU ,  Tomohisa KOIKE

IPC分类号： B41J2/325

CPC分类号： B41J2/325

摘要： A printing system and printing apparatus are provided with improvements in the image quality of an image formed on a printing medium, a peel off region (PO) wherein a transfer layer of a transfer film is not transferred is set corresponding to a card, modified printing data is generated by modifying a gray-scale value of printing data inside a region that is larger than the PO region by predetermined dimensions and including the PO region in the printing data of Y, M, C and Bk into a gray-scale value of 0, an image is formed on the transfer film by heating a thermal head for an image formation panel of an ink ribbon according to the modified printing data. The transfer layer is peeled off by heating the thermal head for a peel off panel of the ink ribbon according to position information of the PO region.

摘要翻译： 提供一种打印系统和打印设备，其对打印介质上形成的图像的图像质量进行改进，对应于卡设置转印膜的未转印转印层的剥离区域（PO），修改印刷 通过将大于PO区域的区域内的打印数据的灰度值修改为预定尺寸并且将Y，M，C和Bk的打印数据中的PO区域包括在灰度值的灰度值中来生成数据 0，通过根据修改的打印数据加热色带的图像形成面板的热敏头来在转印膜上形成图像。 根据PO区域的位置信息，通过加热墨带的剥离板的热敏头来剥离转印层。

公开(公告)号：US20130094114A1

公开(公告)日：2013-04-18

申请号：US13612664

申请日：2012-09-12

申请人： Naoki SHIMIZU

发明人： Naoki SHIMIZU

IPC分类号： H02H3/08

CPC分类号： H03K17/567 ,  H03K17/082

摘要： A control apparatus for a switching device which suppresses surge voltages at the time of current shutoff of a switching device to protect from overcurrents although the switching device is not in an overcurrent state, including a current sensor, a comparator, a timer latch, a control circuit, and a transistor. The current sensor detects the current of a switching device and outputs a detected voltage. The comparator outputs a signal when the detected voltage is equal to or greater than a reference voltage. When the time duration of the output signal is equal to or greater than a setting time, the timer latch outputs a surge suppression detection signal, based on which the control circuit outputs to the transistor a driving signal to turn off the switching device. The reference voltage is smaller than a reference voltage used when detecting an overcurrent flowing in the switching device.

摘要翻译： 一种用于开关装置的控制装置，其抑制开关装置的电流切断时的浪涌电压，以防止开关器件不处于过电流状态，包括电流传感器，比较器，定时器锁存器，控制器 电路和晶体管。 电流传感器检测开关器件的电流并输出检测到的电压。 当检测电压等于或大于参考电压时，比较器输出信号。 当输出信号的持续时间等于或大于设定时间时，定时器锁存器输出浪涌抑制检测信号，基于该脉冲抑制检测信号，控制电路向晶体管输出驱动信号以关闭开关器件。 参考电压小于检测在开关装置中流过的过电流时使用的基准电压。

公开(公告)号：US20160019941A1

公开(公告)日：2016-01-21

申请号：US14871063

申请日：2015-09-30

申请人： Naoki SHIMIZU

发明人： Naoki SHIMIZU

IPC分类号： G11C11/16

CPC分类号： G11C11/1653 ,  G11C7/1093 ,  G11C8/10 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0061 ,  G11C13/0069

摘要： A semiconductor memory device includes: banks each including a memory cell array; word lines connected to rows of each of the banks; an address latch circuit configured to latch a full address for specifying one of the word lines, the full address including a first address and a second address; and a control circuit configured to ignore a reset operation for the first address as a target of a set operation, and overwrite the first address in accordance with the set operation when receiving a first command for specifying a reset operation for a bank and a set operation for the first address.