公开(公告)号：US20090166839A1

公开(公告)日：2009-07-02

申请号：US12342603

申请日：2008-12-23

申请人： Naoki Suzuki ,  Akihisa Nakahashi ,  Haneo Iwamoto ,  Manabu Gokan ,  Satoru Yuhaku

发明人： Naoki Suzuki ,  Akihisa Nakahashi ,  Haneo Iwamoto ,  Manabu Gokan ,  Satoru Yuhaku

IPC分类号： H01L23/48 ,  H01L21/02

CPC分类号： H01L25/0657 ,  H01L24/48 ,  H01L24/49 ,  H01L24/50 ,  H01L24/73 ,  H01L24/86 ,  H01L24/91 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/49 ,  H01L2224/73219 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06579 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07811 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A semiconductor stack device having semiconductor chips stacked therein, wherein pads 4d of an uppermost semiconductor chip 2d are disposed on the side of a base substrate 1, and the pads 4d of the semiconductor chip 2d and electrodes 8d of the base substrate 1 are connected to each other via a flexible substrate 5 having circuit components 7 mounted thereon.

摘要翻译： 具有堆叠在其中的半导体芯片的半导体堆叠器件，其中最上半导体芯片2d的焊盘4d设置在基底衬底1的一侧，半导体芯片2d的焊盘4d和基底衬底1的电极8d连接到 彼此通过安装在其上的电路元件7的柔性基板5。

公开(公告)号：US07875974B2

公开(公告)日：2011-01-25

申请号：US12337267

申请日：2008-12-17

申请人： Manabu Gokan ,  Akihisa Nakahashi ,  Naoki Suzuki ,  Haneo Iwamoto ,  Satoru Yuhaku

发明人： Manabu Gokan ,  Akihisa Nakahashi ,  Naoki Suzuki ,  Haneo Iwamoto ,  Satoru Yuhaku

IPC分类号： H01L23/34

CPC分类号： G11C5/02 ,  G11C5/04 ,  G11C5/063 ,  H01L23/5387 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2225/06579 ,  H01L2924/15311 ,  H01L2924/15331

摘要： To provide a stacked mounting structure in which the number of semiconductor chips that can be stacked is greater than conventionally, as well as a method for fabricating the same, each semiconductor chip has electrodes provided at least at one end in the stacked mounting structure, and a board holding the semiconductor chips at the one end is folded with at least two of the semiconductor chips being stacked so as to at least partially overlap with each other.

摘要翻译： 为了提供其中可堆叠的半导体芯片的数量大于常规的堆叠安装结构以及其制造方法，每个半导体芯片具有设置在堆叠的安装结构中的至少一端，并且 将一端保持半导体芯片的板折叠成至少两个半导体芯片被堆叠成至少部分地彼此重叠。

公开(公告)号：US20090166838A1

公开(公告)日：2009-07-02

申请号：US12337267

申请日：2008-12-17

申请人： Manabu Gokan ,  Akihisa Nakahashi ,  Naoki Suzuki ,  Haneo Iwamoto ,  Satoru Yuhaku

发明人： Manabu Gokan ,  Akihisa Nakahashi ,  Naoki Suzuki ,  Haneo Iwamoto ,  Satoru Yuhaku

IPC分类号： H01L23/13

CPC分类号： G11C5/02 ,  G11C5/04 ,  G11C5/063 ,  H01L23/5387 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2225/06579 ,  H01L2924/15311 ,  H01L2924/15331

摘要： To provide a stacked mounting structure in which the number of semiconductor chips that can be stacked is greater than conventionally, as well as a method for fabricating the same, each semiconductor chip has electrodes provided at least at one end in the stacked mounting structure, and a board holding the semiconductor chips at the one end is folded with at least two of the semiconductor chips being stacked so as to at least partially overlap with each other.

摘要翻译： 为了提供其中可堆叠的半导体芯片的数量大于常规的堆叠安装结构以及其制造方法，每个半导体芯片具有设置在堆叠的安装结构中的至少一端，并且 将一端保持半导体芯片的板折叠成至少两个半导体芯片被堆叠成至少部分地彼此重叠。

公开(公告)号：US20080185731A1

公开(公告)日：2008-08-07

申请号：US12022234

申请日：2008-01-30

申请人： Manabu Gokan ,  Akihisa Nakahashi ,  Koichi Nagai ,  Naoki Suzuki

发明人： Manabu Gokan ,  Akihisa Nakahashi ,  Koichi Nagai ,  Naoki Suzuki

IPC分类号： H01L23/498 ,  H01L21/58

CPC分类号： H01L25/0657 ,  G11C5/02 ,  H01L23/3157 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0652 ,  H01L25/105 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2225/06586 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/0106 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/30105 ,  H01L2224/0401 ,  H01L2924/00

摘要： A stacked structure of semiconductor chips includes plural stacked semiconductor chips and plural tabular holding members which hold the respective semiconductor chips. At least two holding members among the holding members are arranged in places at ends of the semiconductor chips where inner side facets of the holding members are opposed to each other, at least one semiconductor chip of the two semiconductor chips held by the two holding members, respectively, is held by only one holding member of the holding members at one end of the semiconductor chip, and all or a part of the one semiconductor chip is arranged in the largest space positioned in an inner side of the inner side facet of the other holding member of the holding members, the largest space being formed by a surface including the one surface of the other holding member, a surface including the other surface of the other holding member, and a surface including a surface of the other semiconductor chip held by the other holding member, the other semiconductor chip being closer to the other holding member.

摘要翻译： 半导体芯片的堆叠结构包括多个堆叠半导体芯片和保持各个半导体芯片的多个平板状保持构件。 保持构件中的至少两个保持构件布置在保持构件的内侧面彼此相对的半导体芯片的端部的位置处，由两个保持构件保持的两个半导体芯片中的至少一个半导体芯片， 分别由半导体芯片的一端的保持构件的一个保持构件保持，并且一个半导体芯片的全部或一部分配置在位于另一个的内侧面的内侧的最大空间 保持构件的保持构件，由包括另一个保持构件的一个表面的表面形成的最大空间，包括另一个保持构件的另一个表面的表面以及包括由另一个保持构件的另一个表面保持的另一个半导体芯片的表面的表面 另一个保持构件，另一个半导体芯片更靠近另一个保持构件。

公开(公告)号：US07808094B2

公开(公告)日：2010-10-05

申请号：US12022234

申请日：2008-01-30

申请人： Manabu Gokan ,  Akihisa Nakahashi ,  Koichi Nagai ,  Naoki Suzuki

发明人： Manabu Gokan ,  Akihisa Nakahashi ,  Koichi Nagai ,  Naoki Suzuki

IPC分类号： H01L23/02

CPC分类号： H01L25/0657 ,  G11C5/02 ,  H01L23/3157 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0652 ,  H01L25/105 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2225/06586 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/0106 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/30105 ,  H01L2224/0401 ,  H01L2924/00

摘要： A stacked structure of semiconductor chips includes plural stacked semiconductor chips and plural tabular holding members which hold the respective semiconductor chips. At least two holding members among the holding members are arranged in places at ends of the semiconductor chips where inner side facets of the holding members are opposed to each other, at least one semiconductor chip of the two semiconductor chips held by the two holding members, respectively, is held by only one holding member of the holding members at one end of the semiconductor chip, and all or a part of the one semiconductor chip is arranged in the largest space positioned in an inner side of the inner side facet of the other holding member of the holding members, the largest space being formed by a surface including the one surface of the other holding member, a surface including the other surface of the other holding member, and a surface including a surface of the other semiconductor chip held by the other holding member, the other semiconductor chip being closer to the other holding member.

摘要翻译： 半导体芯片的堆叠结构包括多个堆叠半导体芯片和保持各个半导体芯片的多个平板状保持构件。 保持构件中的至少两个保持构件布置在保持构件的内侧面彼此相对的半导体芯片的端部的位置处，由两个保持构件保持的两个半导体芯片中的至少一个半导体芯片， 分别由半导体芯片的一端的保持构件的一个保持构件保持，并且一个半导体芯片的全部或一部分配置在位于另一个的内侧面的内侧的最大空间 保持构件的保持构件，由包括另一个保持构件的一个表面的表面形成的最大空间，包括另一个保持构件的另一个表面的表面以及包括由另一个保持构件的另一个表面保持的另一个半导体芯片的表面的表面 另一个保持构件，另一个半导体芯片更靠近另一个保持构件。

公开(公告)号：US08093505B2

公开(公告)日：2012-01-10

申请号：US12438570

申请日：2007-08-10

申请人： Manabu Gokan ,  Akihisa Nakahashi ,  Takayuki Hirose ,  Yoko Kasai ,  Kohichi Tanda

发明人： Manabu Gokan ,  Akihisa Nakahashi ,  Takayuki Hirose ,  Yoko Kasai ,  Kohichi Tanda

IPC分类号： H05K1/00

CPC分类号： H05K1/144 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/19105 ,  H01L2924/3025 ,  H05K1/023 ,  H05K1/145 ,  H05K3/323 ,  H05K3/361 ,  H05K3/403 ,  H05K2201/0367 ,  H05K2201/042 ,  H05K2201/09181 ,  H05K2201/10234 ,  H05K2201/10287 ,  Y10T29/49117 ,  H01L2224/0401

摘要： Provided is a layered electronic circuit device capable of realizing high-density/high-function mounting, easily inspecting and repairing the respective constituent elements, and improving the electronic connection characteristic. The layered electronic circuit device includes a first circuit substrate (101) and a second circuit substrate (102) which are arranged in parallel such that their substrate surfaces are opposed to each other. The peripheral portion of the first circuit substrate (101) and the peripheral portion of the second circuit substrate (102) are connected to each other by connection members (10a to 10d) having a wiring member (103) and a thermal hardening anisotropic conductive sheet (107), thereby performing electric connection.

摘要翻译： 提供一种能够实现高密度/高功能安装，容易地检查和修复各个组成元件以及改善电子连接特性的分层电子电路装置。 分层电子电路器件包括平行布置以使得它们的衬底表面彼此相对的第一电路衬底（101）和第二电路衬底（102）。 第一电路基板（101）的周边部分和第二电路基板（102）的周边部分通过具有布线部件（103）和热硬化各向异性导电片的连接部件（10a〜10d）彼此连接 （107），从而进行电连接。

公开(公告)号：US20100230147A1

公开(公告)日：2010-09-16

申请号：US12438570

申请日：2007-08-10

申请人： Manabu Gokan ,  Akihisa Nakahashi ,  Takayuki Hirose ,  Yoko Kasai ,  Kohichi Tanda

发明人： Manabu Gokan ,  Akihisa Nakahashi ,  Takayuki Hirose ,  Yoko Kasai ,  Kohichi Tanda

IPC分类号： H05K1/00 ,  H05K1/14

CPC分类号： H05K1/144 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/19105 ,  H01L2924/3025 ,  H05K1/023 ,  H05K1/145 ,  H05K3/323 ,  H05K3/361 ,  H05K3/403 ,  H05K2201/0367 ,  H05K2201/042 ,  H05K2201/09181 ,  H05K2201/10234 ,  H05K2201/10287 ,  Y10T29/49117 ,  H01L2224/0401

摘要： Provided is a layered electronic circuit device capable of realizing high-density/high-function mounting, easily inspecting and repairing the respective constituent elements, and improving the electronic connection characteristic. The layered electronic circuit device includes a first circuit substrate (101) and a second circuit substrate (102) which are arranged in parallel such that their substrate surfaces are opposed to each other. The peripheral portion of the first circuit substrate (101) and the peripheral portion of the second circuit substrate (102) are connected to each other by connection members (10a to 10d) having a wiring member (103) and a thermal hardening anisotropic conductive sheet (107), thereby performing electric connection.

摘要翻译： 提供一种能够实现高密度/高功能安装，容易地检查和修复各个组成元件以及改善电子连接特性的分层电子电路装置。 分层电子电路器件包括平行布置以使得它们的衬底表面彼此相对的第一电路衬底（101）和第二电路衬底（102）。 第一电路基板（101）的周边部分和第二电路基板（102）的周边部分通过具有布线部件（103）和热硬化各向异性导电片的连接部件（10a〜10d）彼此连接 （107），从而进行电连接。

公开(公告)号：US07638888B2

公开(公告)日：2009-12-29

申请号：US12031363

申请日：2008-02-14

申请人： Naoki Suzuki ,  Akihisa Nakahashi ,  Yukihiro Maegawa

发明人： Naoki Suzuki ,  Akihisa Nakahashi ,  Yukihiro Maegawa

IPC分类号： H01L23/544

CPC分类号： H01L23/544 ,  H01L23/13 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/45014 ,  H01L2224/4899 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0106 ,  H01L2924/01078 ,  Y10T29/49128 ,  H01L2224/45099 ,  H01L2224/05599

摘要： There is provided a semiconductor chip mounting substrate including a substrate on which a mounting region for mounting a semiconductor chip and a connection region for interlayer connection of the semiconductor chip are formed, and a plurality of alignment marks for alignment at the time of stacking which are provided around or in the connection region on the substrate, wherein a reinforcing member as a reinforcing region for reinforcing a portion between the plurality of alignment marks is provided on the substrate.

摘要翻译： 提供了一种半导体芯片安装基板，包括：基板，其上形成有用于安装半导体芯片的安装区域和用于半导体芯片的层间连接的连接区域;以及多个在堆叠时对准的对准标记， 设置在基板的周围或连接区域中，其中，作为用于加强多个对准标记之间的部分的加强区域的加强构件设置在基板上。

公开(公告)号：US20080197471A1

公开(公告)日：2008-08-21

申请号：US12031363

申请日：2008-02-14

申请人： Naoki Suzuki ,  Akihisa Nakahashi ,  Yukihiro Maegawa

发明人： Naoki Suzuki ,  Akihisa Nakahashi ,  Yukihiro Maegawa

IPC分类号： H01L23/48 ,  H01L23/544 ,  H05K3/00

CPC分类号： H01L23/544 ,  H01L23/13 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/45014 ,  H01L2224/4899 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0106 ,  H01L2924/01078 ,  Y10T29/49128 ,  H01L2224/45099 ,  H01L2224/05599

摘要： There is provided a semiconductor chip mounting substrate including a substrate on which a mounting region for mounting a semiconductor chip and a connection region for interlayer connection of the semiconductor chip are formed, and a plurality of alignment marks for alignment at the time of stacking which are provided around or in the connection region on the substrate, wherein a reinforcing member as a reinforcing region for reinforcing a portion between the plurality of alignment marks is provided on the substrate.

摘要翻译： 提供了一种半导体芯片安装基板，包括：基板，其上形成有用于安装半导体芯片的安装区域和用于半导体芯片的层间连接的连接区域;以及多个在堆叠时对准的对准标记， 设置在基板的周围或连接区域中，其中，作为用于加强多个对准标记之间的部分的加强区域的加强构件设置在基板上。

公开(公告)号：US08283661B2

公开(公告)日：2012-10-09

申请号：US13130408

申请日：2010-04-20

申请人： Kazutoshi Miyazawa ,  Akihisa Nakahashi

发明人： Kazutoshi Miyazawa ,  Akihisa Nakahashi

IPC分类号： H01L29/08 ,  H01L35/24 ,  H01L51/00 ,  H01L29/18 ,  H01L33/00 ,  H01L29/20 ,  H01L29/22 ,  H01L29/227 ,  H01L31/00 ,  H01L21/00 ,  H01L51/40

CPC分类号： H01L51/56 ,  H01L27/322 ,  H01L27/3244 ,  H01L51/5203 ,  H01L2251/5315 ,  H01L2251/568

摘要： Provided is an organic EL display manufacturing method which has: a step wherein an organic EL panel having a substrate and organic EL elements arranged in matrix on the substrate is prepared, and each organic EL element is permitted to have a pixel electrode disposed on the substrate, an organic layer disposed on the pixel electrode, a transparent counter electrode disposed on the organic layer, a sealing layer disposed on the transparent counter electrode, and a color filter disposed on the sealing layer; a step of detecting a defective portion on the organic layer in the organic EL element; and a step of breaking the transparent counter electrode in a region on the defective portion of the transparent counter electrode by irradiating the region on the defective portion with a laser beam. The laser beam is radiated by being tilted with respect to the normal line on the display surface of the organic EL panel.

摘要翻译： 提供了一种有机EL显示器制造方法，其具有以下步骤：制备具有衬底的有机EL面板和在衬底上以矩阵形式布置的有机EL元件的步骤，并且允许每个有机EL元件具有设置在衬底上的像素电极 设置在像素电极上的有机层，设置在有机层上的透明对电极，设置在透明对电极上的密封层和设置在密封层上的滤色器; 检测有机EL元件中有机层上的缺陷部分的步骤; 以及通过用激光束照射缺陷部分上的区域来在透明对电极的缺陷部分的区域中破坏透明对电极的步骤。 通过相对于有机EL面板的显示面上的法线倾斜来激发激光束。